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Kestrel Collaboration
Kestrel LiteX
litex-boards
Commits
19d0b958
Commit
19d0b958
authored
Jul 22, 2020
by
Florent Kermarrec
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platforms/targets: keep in sync with litex.
parent
0ee4b215
Changes
2
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2 changed files
with
1 addition
and
2 deletions
+1
-2
litex_boards/platforms/nexys4ddr.py
litex_boards/platforms/nexys4ddr.py
+1
-0
litex_boards/targets/nexys_video.py
litex_boards/targets/nexys_video.py
+0
-2
No files found.
litex_boards/platforms/nexys4ddr.py
View file @
19d0b958
...
...
@@ -73,6 +73,7 @@ _io = [
Subsignal
(
"data"
,
Pins
(
"C2 E1 F1 D2"
),
Misc
(
"PULLUP True"
)),
Subsignal
(
"cmd"
,
Pins
(
"C1"
),
Misc
(
"PULLUP True"
)),
Subsignal
(
"clk"
,
Pins
(
"B1"
)),
Subsignal
(
"cd"
,
Pins
(
"A1"
)),
Misc
(
"SLEW=FAST"
),
IOStandard
(
"LVCMOS33"
),
),
...
...
litex_boards/targets/nexys_video.py
View file @
19d0b958
...
...
@@ -30,7 +30,6 @@ class _CRG(Module):
self
.
clock_domains
.
cd_sys4x_dqs
=
ClockDomain
(
reset_less
=
True
)
self
.
clock_domains
.
cd_clk200
=
ClockDomain
()
self
.
clock_domains
.
cd_clk100
=
ClockDomain
()
self
.
clock_domains
.
cd_sd
=
ClockDomain
()
# # #
...
...
@@ -42,7 +41,6 @@ class _CRG(Module):
pll
.
create_clkout
(
self
.
cd_sys4x_dqs
,
4
*
sys_clk_freq
,
phase
=
90
)
pll
.
create_clkout
(
self
.
cd_clk200
,
200e6
)
pll
.
create_clkout
(
self
.
cd_clk100
,
100e6
)
pll
.
create_clkout
(
self
.
cd_sd
,
10e6
)
self
.
submodules
.
idelayctrl
=
S7IDELAYCTRL
(
self
.
cd_clk200
)
...
...
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