Commit 11405d9e authored by Florent Kermarrec's avatar Florent Kermarrec

targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to...

targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
parent 1fcd9697
...@@ -61,11 +61,11 @@ class _CRG(Module): ...@@ -61,11 +61,11 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_etherbone=False, eth_ip="192.168.1.50", **kwargs): def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", **kwargs):
platform = sds1104xe.Platform() platform = sds1104xe.Platform()
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial": if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART. kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self, platform, sys_clk_freq, SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Siglent SDS1104X-E", ident = "LiteX SoC on Siglent SDS1104X-E",
......
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