diff --git a/litex_boards/platforms/alveo_u280.py b/litex_boards/platforms/alveo_u280.py index 7499072126e78061d5993e95b9b7e1548a3f2b9a..e93e64ca7405112e9f06ffc8a4b580e61aaabe19 100644 --- a/litex_boards/platforms/alveo_u280.py +++ b/litex_boards/platforms/alveo_u280.py @@ -1,12 +1,10 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2020 David Shah -# Copyright (c) 2020 Florent Kermarrec +# Copyright (c) 2021 Sergiu Mosanu +# # SPDX-License-Identifier: BSD-2-Clause -# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525 and Alveo U250 - from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc from litex.build.xilinx import XilinxPlatform, VivadoProgrammer @@ -31,12 +29,12 @@ _io = [ ("gpio_led", 2, Pins("D31"), IOStandard("LVCMOS18")), # Switches - + ("gpio_sw", 0, Pins("J30"), IOStandard("LVCMOS18")), ("gpio_sw", 1, Pins("J32"), IOStandard("LVCMOS18")), ("gpio_sw", 2, Pins("K32"), IOStandard("LVCMOS18")), ("gpio_sw", 3, Pins("K31"), IOStandard("LVCMOS18")), - + # Serial ("serial", 0, Subsignal("rx", Pins("A28"), IOStandard("LVCMOS18")), diff --git a/litex_boards/targets/alveo_u280.py b/litex_boards/targets/alveo_u280.py index f56b74ffaec30339897ad625b5e6df65e9cb2562..daccffe7bcb2a0ba20d11bdcaba20137b5e9499c 100755 --- a/litex_boards/targets/alveo_u280.py +++ b/litex_boards/targets/alveo_u280.py @@ -3,10 +3,8 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2020 Fei Gao -# Copyright (c) 2020 Florent Kermarrec -# Copyright (c) 2020 David Shah -# Modified for Alveo U280 by Sergiu Mosanu based on XCU1525 and Alveo U250 +# Copyright (c) 2021 Sergiu Mosanu +# # SPDX-License-Identifier: BSD-2-Clause import argparse, os @@ -44,7 +42,7 @@ class _CRG(Module): self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_idelay, 500e6, with_reset=False) + pll.create_clkout(self.cd_idelay, 500e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. self.specials += [