Merge pull request #130 from antmicro/fix-zybo-clock-pin

zybo_z7: fix clock pin constraint

Merge pull request #130 from antmicro/fix-zybo-clock-pin
zybo_z7: fix clock pin constraint
0b8a01f9 · enjoy-digital · GitHub · 26d3b572 · f66860c2 · 0b8a01f9
Unverified Commit 0b8a01f9 authored Dec 07, 2020 by enjoy-digital Committed by GitHub Dec 07, 2020
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litex_boards/platforms/zybo_z7.py litex_boards/platforms/zybo_z7.py +1 -1

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--- a/litex_boards/platforms/zybo_z7.py
+++ b/litex_boards/platforms/zybo_z7.py
@@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer

 _io = [
    # Clk / Rst
-    ("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
+    ("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),

    # Leds
    ("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),