Unverified Commit 0b8a01f9 authored by enjoy-digital's avatar enjoy-digital Committed by GitHub

Merge pull request #130 from antmicro/fix-zybo-clock-pin

zybo_z7: fix clock pin constraint
parents 26d3b572 f66860c2
......@@ -11,7 +11,7 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# Clk / Rst
("clk125", 0, Pins("L16"), IOStandard("LVCMOS33")),
("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),
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