targets/orangecrab: use new DM remapping capability of LiteDRAM to fix LDM/UDM.

Required by VexRiscv-SMP that uses DMs on LiteDRAM interface.

litex_boards/targets/orangecrab.py

@@ -180,7 +180,8 @@ class BaseSoC(SoCCore):
             ddram_pads = platform.request("ddram")
             self.submodules.ddrphy = ECP5DDRPHY(
                 pads         = ddram_pads,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                dm_remapping = {0:1, 1:0})
             self.ddrphy.settings.rtt_nom = "disabled"
             self.add_csr("ddrphy")
             if hasattr(ddram_pads, "vccio"):