litex_boards/platforms/zybo_z7.py · 0b8a01f929317a42e167c006b95d39026f9acac3 · Kestrel Collaboration / Kestrel LiteX / litex-boards · GitLab

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zybo_z7: fix clock pin constraint · f66860c2
Alessandro Comodi authored Dec 07, 2020
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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f66860c2

zybo_z7.py 3.39 KB

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