arty_s7.py 4.55 KB
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#!/usr/bin/env python3

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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>,
# Copyright (c) 2020 Staf Verhaegen <staf@fibraservi.eu>
# SPDX-License-Identifier: BSD-2-Clause
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import os
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import argparse

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from migen import *
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from litex_boards.platforms import arty_s7
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from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict

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from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
    def __init__(self, platform, sys_clk_freq):
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        self.rst = Signal()
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        self.clock_domains.cd_sys       = ClockDomain()
        self.clock_domains.cd_sys2x     = ClockDomain(reset_less=True)
        self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
        self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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        self.clock_domains.cd_idelay    = ClockDomain()
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        # # #

        self.submodules.pll = pll = S7PLL(speedgrade=-1)
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        self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
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        pll.register_clkin(platform.request("clk100"), 100e6)
        pll.create_clkout(self.cd_sys,       sys_clk_freq)
        pll.create_clkout(self.cd_sys2x,     2*sys_clk_freq)
        pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
        pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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        pll.create_clkout(self.cd_idelay,    200e6)
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        self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
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# BaseSoC ------------------------------------------------------------------------------------------

class BaseSoC(SoCCore):
    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
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        platform = arty_s7.Platform()
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        # SoCCore ----------------------------------------------------------------------------------
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        SoCCore.__init__(self, platform, sys_clk_freq,
            ident          = "LiteX SoC on Arty S7",
            ident_version  = True,
            **kwargs)
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        # CRG --------------------------------------------------------------------------------------
        self.submodules.crg = _CRG(platform, sys_clk_freq)

        # DDR3 SDRAM -------------------------------------------------------------------------------
        if not self.integrated_main_ram_size:
            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
                memtype        = "DDR3",
                nphases        = 4,
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                sys_clk_freq   = sys_clk_freq)
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            self.add_csr("ddrphy")
            self.add_sdram("sdram",
                phy                     = self.ddrphy,
                module                  = MT41K128M16(sys_clk_freq, "1:4"),
                origin                  = self.mem_map["main_ram"],
                size                    = kwargs.get("max_sdram_size", 0x40000000),
                l2_cache_size           = kwargs.get("l2_size", 8192),
                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
                l2_cache_reverse        = True
            )

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        # Leds -------------------------------------------------------------------------------------
        self.submodules.leds = LedChaser(
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            pads         = platform.request_all("user_led"),
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            sys_clk_freq = sys_clk_freq)
        self.add_csr("leds")

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# Build --------------------------------------------------------------------------------------------

def main():
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    parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7")
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    parser.add_argument("--build",        action="store_true", help="Build bitstream")
    parser.add_argument("--load",         action="store_true", help="Load bitstream")
    parser.add_argument("--sys-clk-freq", default=100e6,       help="System clock frequency (default: 100MHz)")
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    builder_args(parser)
    soc_sdram_args(parser)
    vivado_build_args(parser)
    args = parser.parse_args()

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    soc = BaseSoC(
        sys_clk_freq = int(float(args.sys_clk_freq)),
        **soc_sdram_argdict(args)
    )
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    builder = Builder(soc, **builder_argdict(args))
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    builder.build(**vivado_build_argdict(args), run=args.build)
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    if args.load:
        prog = soc.platform.create_programmer()
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        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
    main()