Add module name CLI option

phy/usddrphy: use ic reset (to be sure to follow UG571's reset sequence) and use VAR_LOAD mode on DQS's ODELAYE3.

This fixes some reset issues seen on some boards (seen when deployed on large systems with > 100 different boards/controllers),
and avoid having to reload DQS delay from software on DQS reset.

init: make the write leveling MR bit configurable

Allow to pass all module timings in the format (ck, ns)

test: improve error messages when comparing files in test_init.py

Add customizable standalone user port data widths

phy/ecp5ddrphy: add clk_polarity parameter to allow inverting clk polarity (for boards with clk_p/n swapped).

modules: add IS43TR16256A support.

phy/ecp5ddrphy: remove dm_remapping introduce for VexRiscv-SMP on OrangeCrab: we can now use Wishbone/L2.

phy/usddrphy: simplify tCK reference by using a specific ODELAYE3 in FIXED mode and keep the PHY in reset by default.

Keeping the PHY in reset by default was not possible previously due to the ODELAYE3 configuration
that was lost on reset. Using a specific ODELAYE3 in FIXED mode allow keeping the PHY in reset at
startup.

Allow adding a delay on Clock/Commands. Delay is manual for now but could be
automated in the future if useful (as done on 7-series/Ultrascale(+)).

One some hardware, forcing cl or/and cwl to non-default values can provide
better results.

common: rename get_cl_cw function to get_default_cl_cwl (and provide retro-compat) and add get_default_cl, get_default_cwl functions.

modules: add MT48LC32M8 SDR module

Required on OrangeCrab that has LDM/UDM swapped.