modules: add MT48LC32M8 SDR module

ec37a635 · Nathaniel R. Lewis · Michael Pye · 103072c6 · ec37a635
Unverified Commit ec37a635 authored Nov 15, 2020 by Nathaniel R. Lewis Committed by Michael Pye Dec 31, 2020
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litedram/modules.py litedram/modules.py +9 -0

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--- a/litedram/modules.py
+++ b/litedram/modules.py
@@ -461,6 +461,15 @@ class MT48LC16M16(SDRModule):
    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}

+class MT48LC32M8(SDRModule):
+    # geometry
+    nbanks = 4
+    nrows  = 8192
+    ncols  = 1024
+    # timings
+    technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
+    speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
+
 class AS4C16M16(SDRModule):
    # geometry
    nbanks = 4