bench/targets: add identifier.

ea634802 · Florent Kermarrec · c4724991 · ea634802 · ea634802 · ea634802
Commit ea634802 authored Dec 10, 2020 by Florent Kermarrec
Showing with 10 additions and 0 deletions

bench/arty.py bench/arty.py +2 -0

bench/genesys2.py bench/genesys2.py +2 -0

bench/kc705.py bench/kc705.py +2 -0

bench/kcu105.py bench/kcu105.py +2 -0

bench/xcu1525.py bench/xcu1525.py +2 -0

No files found.
--- a/bench/arty.py
+++ b/bench/arty.py
@@ -66,6 +66,8 @@ class BenchSoC(SoCCore):

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident               = "LiteDRAM bench on Arty",
+            ident_version       = True,
            integrated_rom_size = 0x10000,
            integrated_rom_mode = "rw",
            csr_data_width      = 32,

--- a/bench/genesys2.py
+++ b/bench/genesys2.py
@@ -64,6 +64,8 @@ class BenchSoC(SoCCore):

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident               = "LiteDRAM bench on Genesys2",
+            ident_version       = True,
            integrated_rom_size = 0x10000,
            integrated_rom_mode = "rw",
            csr_data_width      = 32,

--- a/bench/kc705.py
+++ b/bench/kc705.py
@@ -64,6 +64,8 @@ class BenchSoC(SoCCore):

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident               = "LiteDRAM bench on KC705",
+            ident_version       = True,
            integrated_rom_size = 0x10000,
            integrated_rom_mode = "rw",
            csr_data_width      = 32,

--- a/bench/kcu105.py
+++ b/bench/kcu105.py
@@ -83,6 +83,8 @@ class BenchSoC(SoCCore):

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident               = "LiteDRAM bench on KCU105",
+            ident_version       = True,
            integrated_rom_size = 0x10000,
            integrated_rom_mode = "rw",
            csr_data_width      = 32,

--- a/bench/xcu1525.py
+++ b/bench/xcu1525.py
@@ -79,6 +79,8 @@ class BenchSoC(SoCCore):

        # SoCCore ----------------------------------------------------------------------------------
        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
+            ident               = "LiteDRAM bench on XCU1525",
+            ident_version       = True,
            integrated_rom_size = 0x10000,
            integrated_rom_mode = "rw",
            csr_data_width      = 32,