common: rename get_cl_cw function to get_default_cl_cwl (and provide...

common: rename get_cl_cw function to get_default_cl_cwl (and provide retro-compat) and add get_default_cl, get_default_cwl functions.

litedram/common.py

@@ -26,7 +26,7 @@ burst_lengths = {
     "DDR4":  8
 }
 
-def get_cl_cw(memtype, tck):
+def get_default_cl_cwl(memtype, tck):
     f_to_cl_cwl = OrderedDict()
     if memtype == "DDR2":
         f_to_cl_cwl[400e6]  = (3, 2)
@@ -53,6 +53,14 @@ def get_cl_cw(memtype, tck):
             return cl, cwl
     raise ValueError
 
+def get_default_cl(memtype, tck):
+    cl, _ = get_default_cl_cwl(memtype, tck)
+    return cl
+
+def get_default_cwl(memtype, tck):
+    _, cwl = get_default_cl_cwl(memtype, tck)
+    return cwl
+
 def get_sys_latency(nphases, cas_latency):
     return math.ceil(cas_latency/nphases)
 

litedram/phy/ecp5ddrphy.py

@@ -127,7 +127,7 @@ class ECP5DDRPHY(Module, AutoCSR):
         self.submodules.init = ECP5DDRPHYInit()
 
         # Parameters -------------------------------------------------------------------------------
-        cl, cwl         = get_cl_cw(memtype, tck)
+        cl, cwl         = get_default_cl_cwl(memtype, tck)
         cl_sys_latency  = get_sys_latency(nphases, cl)
         cwl_sys_latency = get_sys_latency(nphases, cwl)
 

litedram/phy/s7ddrphy.py

@@ -50,7 +50,7 @@ class S7DDRPHY(Module, AutoCSR):
         }
         half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
 
-        cl, cwl         = get_cl_cw(memtype, tck)
+        cl, cwl         = get_default_cl_cwl(memtype, tck)
         cl_sys_latency  = get_sys_latency(nphases, cl)
         cwl_sys_latency = get_sys_latency(nphases, cwl)
         rdphase         = get_sys_phase(nphases, cl_sys_latency,   cl + cmd_latency)

litedram/phy/usddrphy.py

@@ -49,7 +49,7 @@ class USDDRPHY(Module, AutoCSR):
         if phytype == "USDDRPHY":  assert iodelay_clk_freq >= 200e6
         if phytype == "USPDDRPHY": assert iodelay_clk_freq >= 300e6
 
-        cl, cwl         = get_cl_cw(memtype, tck)
+        cl, cwl         = get_default_cl_cwl(memtype, tck)
         cl_sys_latency  = get_sys_latency(nphases, cl)
         cwl_sys_latency = get_sys_latency(nphases, cwl)
         rdphase         = get_sys_phase(nphases, cl_sys_latency,   cl + cmd_latency)