Commit d016edf6 authored by Florent Kermarrec's avatar Florent Kermarrec

frontend/dma: Drive aw/ar.size when using AXI port.

parent 424b5f95
...@@ -9,6 +9,8 @@ ...@@ -9,6 +9,8 @@
"""Direct Memory Access (DMA) reader and writer modules.""" """Direct Memory Access (DMA) reader and writer modules."""
from math import log2
from migen import * from migen import *
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
...@@ -73,6 +75,8 @@ class LiteDRAMDMAReader(Module, AutoCSR): ...@@ -73,6 +75,8 @@ class LiteDRAMDMAReader(Module, AutoCSR):
if is_native: if is_native:
self.comb += cmd.we.eq(0) self.comb += cmd.we.eq(0)
if is_axi:
self.comb += cmd.size.eq(int(log2(port.data_width//8)))
self.comb += [ self.comb += [
cmd.addr.eq(sink.address), cmd.addr.eq(sink.address),
cmd.valid.eq(sink.valid & request_enable), cmd.valid.eq(sink.valid & request_enable),
...@@ -191,6 +195,8 @@ class LiteDRAMDMAWriter(Module, AutoCSR): ...@@ -191,6 +195,8 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
if is_native: if is_native:
self.comb += cmd.we.eq(1) self.comb += cmd.we.eq(1)
if is_axi:
self.comb += cmd.size.eq(int(log2(port.data_width//8)))
self.comb += [ self.comb += [
cmd.addr.eq(sink.address), cmd.addr.eq(sink.address),
cmd.valid.eq(fifo.sink.ready & sink.valid), cmd.valid.eq(fifo.sink.ready & sink.valid),
......
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