From d016edf68b1ee0eef818f42c295625573348f2e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 2 Mar 2021 10:13:59 +0100 Subject: [PATCH] frontend/dma: Drive aw/ar.size when using AXI port. --- litedram/frontend/dma.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py index c4649c5..bc51b6e 100644 --- a/litedram/frontend/dma.py +++ b/litedram/frontend/dma.py @@ -9,6 +9,8 @@ """Direct Memory Access (DMA) reader and writer modules.""" +from math import log2 + from migen import * from litex.soc.interconnect.csr import * @@ -73,6 +75,8 @@ class LiteDRAMDMAReader(Module, AutoCSR): if is_native: self.comb += cmd.we.eq(0) + if is_axi: + self.comb += cmd.size.eq(int(log2(port.data_width//8))) self.comb += [ cmd.addr.eq(sink.address), cmd.valid.eq(sink.valid & request_enable), @@ -191,6 +195,8 @@ class LiteDRAMDMAWriter(Module, AutoCSR): if is_native: self.comb += cmd.we.eq(1) + if is_axi: + self.comb += cmd.size.eq(int(log2(port.data_width//8))) self.comb += [ cmd.addr.eq(sink.address), cmd.valid.eq(fifo.sink.ready & sink.valid), -- 2.30.2