diff --git a/litedram/frontend/dma.py b/litedram/frontend/dma.py
index c4649c504edbdb7dce978e9be1dbf747ae9eada5..bc51b6ed3d4292f380d2a59170758860f2e4e864 100644
--- a/litedram/frontend/dma.py
+++ b/litedram/frontend/dma.py
@@ -9,6 +9,8 @@
 
 """Direct Memory Access (DMA) reader and writer modules."""
 
+from math import log2
+
 from migen import *
 
 from litex.soc.interconnect.csr import *
@@ -73,6 +75,8 @@ class LiteDRAMDMAReader(Module, AutoCSR):
 
         if is_native:
             self.comb += cmd.we.eq(0)
+        if is_axi:
+            self.comb += cmd.size.eq(int(log2(port.data_width//8)))
         self.comb += [
             cmd.addr.eq(sink.address),
             cmd.valid.eq(sink.valid & request_enable),
@@ -191,6 +195,8 @@ class LiteDRAMDMAWriter(Module, AutoCSR):
 
         if is_native:
             self.comb += cmd.we.eq(1)
+        if is_axi:
+            self.comb += cmd.size.eq(int(log2(port.data_width//8)))
         self.comb += [
             cmd.addr.eq(sink.address),
             cmd.valid.eq(fifo.sink.ready & sink.valid),