Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
litedram
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kestrel Collaboration
Kestrel LiteX
litedram
Commits
a87c468a
Commit
a87c468a
authored
Dec 10, 2020
by
Florent Kermarrec
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
bench: use --sys-clk-freq=xy to reconfigure frequency and fix Ultrascale.
parent
efb1975d
Changes
6
Hide whitespace changes
Inline
Side-by-side
Showing
6 changed files
with
44 additions
and
15 deletions
+44
-15
bench/arty.py
bench/arty.py
+3
-3
bench/common.py
bench/common.py
+29
-0
bench/genesys2.py
bench/genesys2.py
+3
-3
bench/kc705.py
bench/kc705.py
+3
-3
bench/kcu105.py
bench/kcu105.py
+3
-3
bench/xcu1525.py
bench/xcu1525.py
+3
-3
No files found.
bench/arty.py
View file @
a87c468a
...
...
@@ -133,7 +133,7 @@ def main():
parser
.
add_argument
(
"--with-analyzer"
,
action
=
"store_true"
,
help
=
"Add Analyzer"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--load-bios"
,
action
=
"store_true"
,
help
=
"Load BIOS"
)
parser
.
add_argument
(
"--s
et-sys-clk"
,
default
=
None
,
help
=
"Set sys_clk
"
)
parser
.
add_argument
(
"--s
ys-clk-freq"
,
default
=
None
,
help
=
"Set sys_clk_freq
"
)
parser
.
add_argument
(
"--test"
,
action
=
"store_true"
,
help
=
"Run Full Bench"
)
args
=
parser
.
parse_args
()
...
...
@@ -149,9 +149,9 @@ def main():
from
common
import
load_bios
load_bios
(
"build/arty/software/bios/bios.bin"
)
if
args
.
s
et_sys_clk
is
not
None
:
if
args
.
s
ys_clk_freq
is
not
None
:
from
common
import
s7_set_sys_clk
s7_set_sys_clk
(
clk_freq
=
float
(
args
.
config
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
s7_set_sys_clk
(
clk_freq
=
float
(
args
.
sys_clk_freq
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
if
args
.
test
:
from
common
import
s7_bench_test
...
...
bench/common.py
View file @
a87c468a
...
...
@@ -284,3 +284,32 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
# # #
bus
.
close
()
def
us_set_sys_clk
(
clk_freq
,
vco_freq
):
import
time
from
litex
import
RemoteClient
bus
=
RemoteClient
()
bus
.
open
()
# # #
# (Re)Configuring sys_clk.
print
(
"Configuring sys_clk to {:3.3f}..."
.
format
(
clk_freq
/
1e6
))
uspll
=
USPLL
(
bus
)
clkout0_clkreg1
=
ClkReg1
(
uspll
.
read
(
0x8
))
vco_div
=
int
(
vco_freq
/
clk_freq
)
clkout0_clkreg1
.
high_time
=
vco_div
//
2
+
vco_div
%
2
clkout0_clkreg1
.
low_time
=
vco_div
//
2
uspll
.
write
(
0x08
,
clkout0_clkreg1
.
pack
())
# Measure/verify sys_clk
duration
=
1
start
=
bus
.
regs
.
crg_sys_clk_counter
.
read
()
time
.
sleep
(
duration
)
end
=
bus
.
regs
.
crg_sys_clk_counter
.
read
()
print
(
"Measured sys_clk: {:3.2f}MHz."
.
format
((
end
-
start
)
/
(
1e6
*
duration
)))
# # #
bus
.
close
()
\ No newline at end of file
bench/genesys2.py
View file @
a87c468a
...
...
@@ -127,7 +127,7 @@ def main():
parser
.
add_argument
(
"--with-analyzer"
,
action
=
"store_true"
,
help
=
"Add Analyzer"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--load-bios"
,
action
=
"store_true"
,
help
=
"Load BIOS"
)
parser
.
add_argument
(
"--s
et-sys-clk"
,
default
=
None
,
help
=
"Set sys_clk
"
)
parser
.
add_argument
(
"--s
ys-clk-freq"
,
default
=
None
,
help
=
"Set sys_clk_freq
"
)
parser
.
add_argument
(
"--test"
,
action
=
"store_true"
,
help
=
"Run Full Bench"
)
args
=
parser
.
parse_args
()
...
...
@@ -143,9 +143,9 @@ def main():
from
common
import
load_bios
load_bios
(
"build/genesys2/software/bios/bios.bin"
)
if
args
.
s
et_sys_clk
is
not
None
:
if
args
.
s
ys_clk_freq
is
not
None
:
from
common
import
s7_set_sys_clk
s7_set_sys_clk
(
clk_freq
=
float
(
args
.
config
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
s7_set_sys_clk
(
clk_freq
=
float
(
args
.
sys_clk_freq
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
if
args
.
test
:
from
common
import
s7_bench_test
...
...
bench/kc705.py
View file @
a87c468a
...
...
@@ -127,7 +127,7 @@ def main():
parser
.
add_argument
(
"--with-analyzer"
,
action
=
"store_true"
,
help
=
"Add Analyzer"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--load-bios"
,
action
=
"store_true"
,
help
=
"Load BIOS"
)
parser
.
add_argument
(
"--s
et-sys-clk"
,
default
=
None
,
help
=
"Set sys_clk
"
)
parser
.
add_argument
(
"--s
ys-clk-freq"
,
default
=
None
,
help
=
"Set sys_clk_freq
"
)
parser
.
add_argument
(
"--test"
,
action
=
"store_true"
,
help
=
"Run Full Bench"
)
args
=
parser
.
parse_args
()
...
...
@@ -143,9 +143,9 @@ def main():
from
common
import
load_bios
load_bios
(
"build/kc705/software/bios/bios.bin"
)
if
args
.
s
et_sys_clk
is
not
None
:
if
args
.
s
ys_clk_freq
is
not
None
:
from
common
import
us_set_sys_clk
us_set_sys_clk
(
clk_freq
=
float
(
args
.
config
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
us_set_sys_clk
(
clk_freq
=
float
(
args
.
sys_clk_freq
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
if
args
.
test
:
from
common
import
s7_bench_test
...
...
bench/kcu105.py
View file @
a87c468a
...
...
@@ -148,7 +148,7 @@ def main():
parser
.
add_argument
(
"--with-analyzer"
,
action
=
"store_true"
,
help
=
"Add Analyzer"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--load-bios"
,
action
=
"store_true"
,
help
=
"Load BIOS"
)
parser
.
add_argument
(
"--s
et-sys-clk"
,
default
=
None
,
help
=
"Set sys_clk
"
)
parser
.
add_argument
(
"--s
ys-clk-freq"
,
default
=
None
,
help
=
"Set sys_clk_freq
"
)
parser
.
add_argument
(
"--test"
,
action
=
"store_true"
,
help
=
"Run Full Bench"
)
args
=
parser
.
parse_args
()
...
...
@@ -164,9 +164,9 @@ def main():
from
common
import
load_bios
load_bios
(
"build/kcu105/software/bios/bios.bin"
)
if
args
.
s
et_sys_clk
is
not
None
:
if
args
.
s
ys_clk_freq
is
not
None
:
from
common
import
us_set_sys_clk
us_set_sys_clk
(
clk_freq
=
float
(
args
.
config
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
us_set_sys_clk
(
clk_freq
=
float
(
args
.
sys_clk_freq
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
if
args
.
test
:
from
common
import
us_bench_test
...
...
bench/xcu1525.py
View file @
a87c468a
...
...
@@ -138,7 +138,7 @@ def main():
parser
.
add_argument
(
"--with-analyzer"
,
action
=
"store_true"
,
help
=
"Add Analyzer"
)
parser
.
add_argument
(
"--load"
,
action
=
"store_true"
,
help
=
"Load bitstream"
)
parser
.
add_argument
(
"--load-bios"
,
action
=
"store_true"
,
help
=
"Load BIOS"
)
parser
.
add_argument
(
"--s
et-sys-clk"
,
default
=
None
,
help
=
"Set sys_clk
"
)
parser
.
add_argument
(
"--s
ys-clk-freq"
,
default
=
None
,
help
=
"Set sys_clk_freq
"
)
parser
.
add_argument
(
"--test"
,
action
=
"store_true"
,
help
=
"Run Full Bench"
)
args
=
parser
.
parse_args
()
...
...
@@ -154,9 +154,9 @@ def main():
from
common
import
load_bios
load_bios
(
"build/xcu1525/software/bios/bios.bin"
)
if
args
.
s
et_sys_clk
is
not
None
:
if
args
.
s
ys_clk_freq
is
not
None
:
from
common
import
us_set_sys_clk
us_set_sys_clk
(
clk_freq
=
float
(
args
.
config
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
us_set_sys_clk
(
clk_freq
=
float
(
args
.
sys_clk_freq
),
vco_freq
=
soc
.
crg
.
main_pll
.
compute_config
()[
"vco"
])
if
args
.
test
:
from
common
import
us_bench_test
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment