Commit a1c5a10f authored by Craig Bishop's avatar Craig Bishop

Add module name CLI option

parent 2d021c84
...@@ -682,6 +682,7 @@ def main(): ...@@ -682,6 +682,7 @@ def main():
parser.set_defaults(output_dir="build") parser.set_defaults(output_dir="build")
parser.add_argument("config", help="YAML config file") parser.add_argument("config", help="YAML config file")
parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation") parser.add_argument("--sim", action='store_true', help="Integrate SDRAMPHYModel in core for simulation")
parser.add_argument("--module-name", default="litedram_core", help="Set Verilog module name")
args = parser.parse_args() args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader) core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
...@@ -715,7 +716,7 @@ def main(): ...@@ -715,7 +716,7 @@ def main():
soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000) soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x8000)
builder = Builder(soc, **builder_arguments) builder = Builder(soc, **builder_arguments)
builder.build(build_name="litedram_core", regular_comb=False) builder.build(build_name=args.module_name, regular_comb=False)
if soc.cpu_type is not None: if soc.cpu_type is not None:
init_filename = "mem.init" init_filename = "mem.init"
......
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