bench: use common load_bios function.

bench/arty.py

@@ -142,8 +142,8 @@ def main():
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 
     if args.load_bios:
-        from common import s7_load_bios
-        s7_load_bios("build/arty/software/bios/bios.bin")
+        from common import load_bios
+        load_bios("build/arty/software/bios/bios.bin")
 
     if args.set_sys_clk is not None:
         from common import s7_set_sys_clk

bench/common.py

@@ -106,6 +106,24 @@ class BenchController:
             self.bus.write(self.bus.mems.rom.base + 4*i, data)
             time.sleep(delay)
 
+def load_bios(bios_filename):
+    from litex import RemoteClient
+
+    bus = RemoteClient()
+    bus.open()
+
+    # # #
+
+    # Load BIOS and reboot SoC.
+    print("Loading BIOS...")
+    ctrl = BenchController(bus)
+    ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
+    ctrl.reboot()
+
+    # # #
+
+    bus.close()
+
 # Bench Test ---------------------------------------------------------------------------------------
 
 def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_timeout=40):
@@ -172,24 +190,6 @@ def s7_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
 
     bus.close()
 
-def s7_load_bios(bios_filename):
-    from litex import RemoteClient
-
-    bus = RemoteClient()
-    bus.open()
-
-    # # #
-
-    # Load BIOS and reboot SoC.
-    print("Loading BIOS...")
-    ctrl = BenchController(bus)
-    ctrl.load_rom(bios_filename, delay=1e-4) # FIXME: delay needed @ 115200bauds.
-    ctrl.reboot()
-
-    # # #
-
-    bus.close()
-
 def s7_set_sys_clk(clk_freq, vco_freq):
     import time
     from litex import RemoteClient
@@ -280,6 +280,7 @@ def us_bench_test(freq_min, freq_max, freq_step, vco_freq, bios_filename, bios_t
                 for c in bus.read(bus.regs.uart_xover_rxtx.addr, 1, burst="fixed"):
                     print("{:c}".format(c), end="")
         print("")
+
     # # #
 
     bus.close()

bench/genesys2.py

@@ -140,8 +140,8 @@ def main():
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 
     if args.load_bios:
-        from common import s7_load_bios
-        s7_load_bios("build/genesys2/software/bios/bios.bin")
+        from common import load_bios
+        load_bios("build/genesys2/software/bios/bios.bin")
 
     if args.set_sys_clk is not None:
         from common import s7_set_sys_clk

bench/kc705.py

@@ -140,8 +140,8 @@ def main():
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 
     if args.load_bios:
-        from common import s7_load_bios
-        s7_load_bios("build/kc705/software/bios/bios.bin")
+        from common import load_bios
+        load_bios("build/kc705/software/bios/bios.bin")
 
     if args.set_sys_clk is not None:
         from common import us_set_sys_clk

bench/kcu105.py

@@ -161,8 +161,8 @@ def main():
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 
     if args.load_bios:
-        from common import s7_load_bios
-        s7_load_bios("build/kcu105/software/bios/bios.bin")
+        from common import load_bios
+        load_bios("build/kcu105/software/bios/bios.bin")
 
     if args.set_sys_clk is not None:
         from common import us_set_sys_clk

bench/xcu1525.py

@@ -151,8 +151,8 @@ def main():
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
 
     if args.load_bios:
-        from common import us_load_bios
-        us_load_bios("build/xcu1525/software/bios/bios.bin")
+        from common import load_bios
+        load_bios("build/xcu1525/software/bios/bios.bin")
 
     if args.set_sys_clk is not None:
         from common import us_set_sys_clk