• Florent Kermarrec's avatar
    phy/usddrphy: Avoid separate ODELAYE3 by avoiding software reset on DQS's ODELAYE3. · 25b64c33
    Florent Kermarrec authored
    The fabric is now maintaining an increment counter for each DQS's ODELAY and software
    use it to revert total increments to 0 (equivalent to a reset).
    Avoiding the separate ODELAYE3 simplifies design constraints since it was often placed
    far from the DRAM pads and thus requiring a LOC constraint to avoid timing violations.
    The software has to use the following sdram_write_leveling_rst_delay function:
    static void sdram_write_leveling_rst_delay(int module) {
    	/* Select module */
    	ddrphy_dly_sel_write(1 << module);
    	/* Reset DQ delay */
    	/* Reset DQS delay */
    	while (ddrphy_wdly_dqs_inc_count_read() != 0) {
    	/* Un-select module */
usddrphy.py 22.6 KB