-
Florent Kermarrec authored
The fabric is now maintaining an increment counter for each DQS's ODELAY and software use it to revert total increments to 0 (equivalent to a reset). Avoiding the separate ODELAYE3 simplifies design constraints since it was often placed far from the DRAM pads and thus requiring a LOC constraint to avoid timing violations. The software has to use the following sdram_write_leveling_rst_delay function: static void sdram_write_leveling_rst_delay(int module) { /* Select module */ ddrphy_dly_sel_write(1 << module); /* Reset DQ delay */ ddrphy_wdly_dq_rst_write(1); /* Reset DQS delay */ while (ddrphy_wdly_dqs_inc_count_read() != 0) { ddrphy_wdly_dqs_inc_write(1); cdelay(100); } /* Un-select module */ ddrphy_dly_sel_write(0); }
25b64c33