Update for latest Aquila HDL

parent 3991a6e6
......@@ -30,7 +30,7 @@ from litex.gen.common import reverse_bytes
from litex.build.io import SDRTristate
class AquilaLPCSlave(Module, AutoCSR):
def __init__(self, platform, pads, endianness="big", adr_offset=0x0, debug_signals=None, lpc_clk_mirror=None):
def __init__(self, platform, pads, clk_freq, endianness="big", adr_offset=0x0, debug_signals=None, lpc_clk_mirror=None):
self.slave_bus = slave_bus = wishbone.Interface(data_width=32, adr_width=30)
self.master_bus = master_bus = wishbone.Interface(data_width=32, adr_width=30)
self.wb_irq = Signal()
......@@ -71,6 +71,9 @@ class AquilaLPCSlave(Module, AutoCSR):
self.lpc_clock = Signal()
self.specials += Instance("aquila_lpc_slave_wishbone",
# Configuration data
p_WISHBONE_BUS_FREQUENCY_HZ = clk_freq,
# Wishbone slave port signals
i_slave_wb_cyc = slave_bus.cyc,
i_slave_wb_stb = slave_bus.stb,
......
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