Break up Wishbone master and master / slave interface files

parent 311bcd73
......@@ -177,4 +177,6 @@ class AquilaLPCSlave(Module, AutoCSR):
@staticmethod
def add_sources(platform):
vdir = get_data_mod("peripheral", "aquilalpc").data_location
platform.add_source(os.path.join(vdir, "lpc_interface.v"))
\ No newline at end of file
platform.add_source(os.path.join(vdir, "wishbone_interface.v"))
platform.add_source(os.path.join(vdir, "lpc_slave.v"))
platform.add_source(os.path.join(vdir, "lpc_master.v"))
\ No newline at end of file
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