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Zephyr Firmware
Commit cd31cfa7 authored by Raptor Engineering Development Team's avatar Raptor Engineering Development Team
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Update firmware for RCS Arctic Tern module support

parent e1756b64
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Showing with 34 additions and 96 deletions
kestrel/src/flash_filesystem.c
View file @ cd31cfa7
......@@ -119,7 +119,7 @@ int write_firmware_to_flash(const char* device_name, int partition_number, const
// Find BMC firmware Flash map area
flash_area = NULL;
for (int i = 0; i < flash_map_entries; i++) {
if (strcmp(flash_map[i].fa_dev_name, "bmc") == 0) {
if (strcmp(flash_map[i].fa_dev_name, device_name) == 0) {
if (flash_map[i].fa_id == partition_number) {
flash_area = &flash_map[i];
break;
......
kestrel/src/kestrel.c
View file @ cd31cfa7
......@@ -179,6 +179,7 @@ typedef struct
uint8_t vdn_smbus_addr;
} cpu_info_t;
static const cpu_info_t g_cpu_info[] = {
#ifdef I2CMASTER1_BASE
{
.index = 0,
.i2c_master = (uint8_t *)I2CMASTER1_BASE,
......@@ -193,6 +194,7 @@ static const cpu_info_t g_cpu_info[] = {
.vdn_smbus_addr = 0x2b,
},
#endif
#ifdef I2CMASTER2_BASE
{
.index = 1,
......@@ -342,56 +344,15 @@ static void reboot(void)
static void display_character(char character, int dp)
{
uint32_t dword;
uint16_t value;
// Switch display into alphanumeric mode
gpio1_out_write(gpio1_out_read() | (0x1 << 18));
// FIXME Only supports numbers for now
switch (character)
{
case '0':
value = 0x003f;
break;
case '1':
value = 0x0006;
break;
case '2':
value = 0x221b;
break;
case '3':
value = 0x220f;
break;
case '4':
value = 0x2226;
break;
case '5':
value = 0x222d;
break;
case '6':
value = 0x223d;
break;
case '7':
value = 0x0007;
break;
case '8':
value = 0x223f;
break;
case '9':
value = 0x222f;
break;
default:
value = 0x0000;
break; // OFF
}
dword = gpio3_out_read();
dword &= ~0x7fff;
dword |= (~(value | ((dp == 0) ? 0x0000 : 0x4000))) & 0x7fff;
gpio3_out_write(dword);
// Write character
gpio2_out_write((gpio2_out_read() & ~0xff) | (character & 0xff));
}
static void host_power_status_changed(void)
{
uint32_t dword;
int power_led_on = 0;
// Set power LED based on host status
......@@ -404,15 +365,17 @@ static void host_power_status_changed(void)
}
// Write power LED status to GPIO register
dword = gpio3_out_read();
dword &= ~(0x1 << 15);
dword |= (~(power_led_on & 0x1) << 15) & 0x8000;
gpio3_out_write(dword);
if (power_led_on) {
gpio2_out_write((gpio2_out_read() & ~(0xff << 24)) | ('I' << 24));
}
else {
gpio2_out_write((gpio2_out_read() & ~(0xff << 24)) | ('O' << 24));
}
}
static void set_led_bank_display(uint8_t bitfield)
{
gpio1_out_write(~bitfield);
gpio1_out_write(bitfield & 0xf);
}
static void display_post_code(uint16_t post_code)
......@@ -473,11 +436,10 @@ static void gpio_init(void)
{
// Set up discrete LED bank
set_led_bank_display(0x00);
gpio1_oe_write(0xff);
gpio1_oe_write(0xf);
// Set up alphanumeric display / power LED
gpio3_out_write(0xffff);
gpio3_oe_write(0xffff);
gpio2_out_write((' ' << 24) | (' ' << 16) | (' ' << 8) | ' ');
}
static void set_lpc_slave_irq_enable(uint8_t enabled)
......@@ -792,11 +754,6 @@ void lpc_slave_isr(void)
}
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_IPMI_BT_STATUS, dword);
// Disable IPMI BT IRQ
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1);
dword &= ~((1 & AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_MASK) << AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_SHIFT);
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1, dword);
// Clear H2B_ATN
dword = 0;
dword |= (1 << IPMI_BT_CTL_H2B_ATN_SHIFT);
......@@ -1236,7 +1193,7 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
uint32_t dword;
static uint8_t unhandled_ipmi_command;
ipmi_response_message_t *response_ptr;
volatile ipmi_response_message_t *response_ptr;
static ipmi_response_message_t response;
static uint8_t request_netfn;
static uint8_t request_lun;
......@@ -1247,15 +1204,6 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
int i;
int irqs_locked = 0;
int key = -1;
if (ipmi_bt_transaction_state != 0) {
// Deactivate interrupts on entering critical section
key = irq_lock();
irqs_locked = 1;
}
#if (WITH_ZEPHYR)
if (ipmi_bt_transaction_state != 0) {
// Temporarily raise service thread priority
......@@ -1579,11 +1527,8 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
}
#if (ENABLE_LPC_FW_CYCLE_DMA)
if (!irqs_locked)
{
// Deactivate interrupts on entering critical section
key = irq_lock();
}
// Deactivate interrupts on entering critical section
int key = irq_lock();
// Disable DMA engine
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1);
......@@ -1648,11 +1593,8 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
}
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_DMA_CONFIG1, dword);
if (!irqs_locked)
{
// Re-activate interupts on exiting critical section
irq_unlock(key);
}
// Re-activate interupts on exiting critical section
irq_unlock(key);
#endif
// Generate response
......@@ -1806,7 +1748,7 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
// Send response
// A full copy is done so as to ensure any potentially sensitive data stored
// in the IPMI BT buffer from a previous request is overwritten
memcpy(response_ptr, &response, sizeof(ipmi_response_message_t));
*response_ptr = response;
// Signal BMC data ready
dword = 0;
......@@ -1824,12 +1766,6 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
if (ENABLE_IPMI_DEBUG) {
printk("[IPMI] Response complete, returning to idle\n");
}
// (Re)enable IPMI BT IRQ
dword = read_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1);
dword |= ((1 & AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_MASK) << AQUILA_LPC_CTL_EN_IPMI_BT_IRQ_SHIFT);
write_aquila_register(HOSTLPCSLAVE_BASE, AQUILA_LPC_REG_CONTROL1, dword);
ipmi_bt_transaction_state = 0;
}
break;
......@@ -1838,13 +1774,6 @@ static int process_host_to_bmc_ipmi_bt_transactions(void)
break;
}
if (irqs_locked)
{
// Re-activate interupts on exiting critical section
irq_unlock(key);
irqs_locked = 0;
}
return 0;
}
......@@ -3752,8 +3681,17 @@ int kestrel_init(void)
display_character('1', 0); // STATUS CODE: 1
#if (WITH_SPI)
// Initialize FPGA Flash controller
tercel_spi_flash_init(FPGASPIFLASHCFG_BASE, FPGASPIFLASH_BASE, 1, 0, 0);
// Detect and print attached host SPI Flash ID
KESTREL_LOG("FPGA SPI flash ID: 0x%08x", read_host_spi_flash_id(FPGASPIFLASHCFG_BASE, FPGASPIFLASH_BASE));
reset_flash_device(FPGASPIFLASHCFG_BASE, FPGASPIFLASH_BASE);
configure_flash_device(FPGASPIFLASHCFG_BASE, FPGASPIFLASH_BASE);
// Initialize BMC Flash controller
tercel_spi_flash_init(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE, 1, 0, 0);
tercel_spi_flash_init(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE, 5, 0, 0);
// Detect and print attached host SPI Flash ID
KESTREL_LOG("BMC SPI flash ID: 0x%08x", read_host_spi_flash_id(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE));
......
kestrel/src/shell.c
View file @ cd31cfa7
// © 2020 - 2021 Raptor Engineering, LLC
// © 2020 - 2022 Raptor Engineering, LLC
//
// Released under the terms of the GPL v3
// See the LICENSE file for full details
......@@ -147,7 +147,7 @@ static int kestrel_shell_cmd_reflash(const struct shell *shell, size_t argc, cha
return write_firmware_to_flash("bmc", 1, main_firmware_buffer.buffer_address, main_firmware_buffer.valid_bytes, 1);
}
else if (strcmp(argv[1], "fpga") == 0) {
return write_firmware_to_flash("bmc", 0, main_firmware_buffer.buffer_address, main_firmware_buffer.valid_bytes, 0);
return write_firmware_to_flash("fpga", 0, main_firmware_buffer.buffer_address, main_firmware_buffer.valid_bytes, 0);
}
else {
shell_print(shell, "%s: Invalid parameter", argv[0]);
......
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