Port bare metal Arctic Tern HDMI transceiver setup to Zephyr firmware

kestrel/src/kestrel.c

@@ -56,6 +56,7 @@ LOG_MODULE_REGISTER(kestrel_core, LOG_LEVEL_DBG);
 
 // Host platform configuration
 #define HOST_PLATFORM_FPGA_I2C_ADDRESS 0x31
+#define HDMI_TRANSCEIVER_I2C_ADDRESS   0x4c
 
 // Limits
 #define FLASH_WRITE_LOCATION_RETRY_LIMIT 5
@@ -64,6 +65,7 @@ LOG_MODULE_REGISTER(kestrel_core, LOG_LEVEL_DBG);
 #define CPU0_I2C_MASTER_BASE_ADDR  I2CMASTER0_BASE
 #define CPU1_I2C_MASTER_BASE_ADDR  I2CMASTER1_BASE
 #define P9PS_I2C_MASTER_BASE_ADDR  I2CMASTER4_BASE
+#define HDMI_I2C_MASTER_BASE_ADDR  I2CMASTER4_BASE
 
 // Front panel interface
 // FIXME: Convert LEDs to device tree
@@ -457,6 +459,50 @@ static void gpio_init(void)
     gpio1_oe_write(gpio1_oe_read() | (0x01 << POWER_LED_OUT_GPIO));
 }
 
+static void configure_hdmi_transceiver(uint8_t *i2c_master_base_addr)
+{
+    // ***** Set up the ITE HDMI transceiver *****
+
+    printf("Setting up HDMI transceiver...");
+    // ***** GENERAL *****
+    // Reset device
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x4, 0x1c);
+
+    // ***** VIDEO *****
+    // Set bank 0
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x0f, 0x08); // 0x0f[1:0] = 0
+
+    // AVMute output
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0xc1, 0x01); // 0xc1[0] = 1
+
+    // Take device out of reset
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x04, 0x00);
+
+    // Enable HDMI transmitter reset
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x61, 0x10);
+
+    // Configure input signal
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x70,
+                            0x00); // RGB mode, I/O latch at TxClk, non-CCIR656, non-embedded sync, single edge, no PCLK delay
+    i2c_write_register_byte(
+        i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x90,
+        0x00); // PG horizontal total = 0, H/V sync provided by external driver, active low VSYNC, active low HSYNC, Data Enable provided by external driver
+
+    // Enable DVI mode (works for HDMI as well, host should configure HDMI later in the boot process)
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0xc0, 0x00); // 0xc0[0] = 0
+
+    // Release HDMI transmitter reset
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0x61, 0x00); // 0x61[4] = 0
+
+    // Un-AVMute output
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0xc1, 0x00); // 0xc1[0] = 0
+
+    // ***** AUDIO *****
+    // Disable audio channel
+    i2c_write_register_byte(i2c_master_base_addr, HDMI_TRANSCEIVER_I2C_ADDRESS, 0xe0, 0x08); // 0xe0[3:0] = 0
+    printf("done!\n");
+}
+
 static void set_lpc_slave_irq_enable(uint8_t enabled)
 {
     if (!enabled)
@@ -3703,6 +3749,9 @@ int kestrel_init(void)
 #endif
     }
 
+    // Set up display output
+    configure_hdmi_transceiver((uint8_t *)HDMI_I2C_MASTER_BASE_ADDR);
+
     main_firmware_buffer.locked = 1;
     main_firmware_buffer.buffer_length = (64 + 2) * 1024LL * 1024LL;
 #if (WITH_ZEPHYR)