Update to current Arctic Tern platform SoC

parent ad70978d
...@@ -60,6 +60,15 @@ LOG_MODULE_REGISTER(kestrel_core, LOG_LEVEL_DBG); ...@@ -60,6 +60,15 @@ LOG_MODULE_REGISTER(kestrel_core, LOG_LEVEL_DBG);
// Limits // Limits
#define FLASH_WRITE_LOCATION_RETRY_LIMIT 5 #define FLASH_WRITE_LOCATION_RETRY_LIMIT 5
// SoC configuration
#define CPU0_I2C_MASTER_BASE_ADDR I2CMASTER0_BASE
#define CPU1_I2C_MASTER_BASE_ADDR I2CMASTER1_BASE
#define P9PS_I2C_MASTER_BASE_ADDR I2CMASTER4_BASE
// Front panel interface
// FIXME: Convert LEDs to device tree
#define POWER_LED_OUT_GPIO 10
extern uint32_t irq_unhandled_vector; extern uint32_t irq_unhandled_vector;
extern uint32_t irq_unhandled_source; extern uint32_t irq_unhandled_source;
extern uint8_t irq_unhandled_vector_valid; extern uint8_t irq_unhandled_vector_valid;
...@@ -179,10 +188,10 @@ typedef struct ...@@ -179,10 +188,10 @@ typedef struct
uint8_t vdn_smbus_addr; uint8_t vdn_smbus_addr;
} cpu_info_t; } cpu_info_t;
static const cpu_info_t g_cpu_info[] = { static const cpu_info_t g_cpu_info[] = {
#ifdef I2CMASTER1_BASE #ifdef CPU0_I2C_MASTER_BASE_ADDR
{ {
.index = 0, .index = 0,
.i2c_master = (uint8_t *)I2CMASTER1_BASE, .i2c_master = (uint8_t *)CPU0_I2C_MASTER_BASE_ADDR,
.i2c_frequency = 100000, .i2c_frequency = 100000,
.vdd_regulator_addr = 0x70, .vdd_regulator_addr = 0x70,
.vdd_regulator_page = 0x00, .vdd_regulator_page = 0x00,
...@@ -195,10 +204,10 @@ static const cpu_info_t g_cpu_info[] = { ...@@ -195,10 +204,10 @@ static const cpu_info_t g_cpu_info[] = {
}, },
#endif #endif
#ifdef I2CMASTER2_BASE #ifdef CPU1_I2C_MASTER_BASE_ADDR
{ {
.index = 1, .index = 1,
.i2c_master = (uint8_t *)I2CMASTER2_BASE, .i2c_master = (uint8_t *)CPU1_I2C_MASTER_BASE_ADDR,
.i2c_frequency = 100000, .i2c_frequency = 100000,
.vdd_regulator_addr = 0x70, .vdd_regulator_addr = 0x70,
.vdd_regulator_page = 0x00, .vdd_regulator_page = 0x00,
...@@ -366,16 +375,18 @@ static void host_power_status_changed(void) ...@@ -366,16 +375,18 @@ static void host_power_status_changed(void)
// Write power LED status to GPIO register // Write power LED status to GPIO register
if (power_led_on) { if (power_led_on) {
gpio1_out_write(gpio1_out_read() | (0x01 << POWER_LED_OUT_GPIO));
gpio2_out_write((gpio2_out_read() & ~(0xff << 24)) | ('I' << 24)); gpio2_out_write((gpio2_out_read() & ~(0xff << 24)) | ('I' << 24));
} }
else { else {
gpio2_out_write((gpio2_out_read() & ~(0xff << 24)) | ('O' << 24)); gpio2_out_write((gpio2_out_read() & ~(0xff << 24)) | ('O' << 24));
gpio1_out_write(gpio1_out_read() & ~(0x01 << POWER_LED_OUT_GPIO));
} }
} }
static void set_led_bank_display(uint8_t bitfield) static void set_led_bank_display(uint8_t bitfield)
{ {
gpio1_out_write(bitfield & 0xf); gpio1_out_write((gpio1_out_read() & ~0xf) | (bitfield & 0xf));
} }
static void display_post_code(uint16_t post_code) static void display_post_code(uint16_t post_code)
...@@ -388,13 +399,13 @@ static void display_post_code(uint16_t post_code) ...@@ -388,13 +399,13 @@ static void display_post_code(uint16_t post_code)
{ {
// IPL complete! // IPL complete!
set_led_bank_display(0); set_led_bank_display(0);
i2c_write_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x00); i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x00);
} }
else if (post_code == 0x0) else if (post_code == 0x0)
{ {
// System offline // System offline
set_led_bank_display(0); set_led_bank_display(0);
i2c_write_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x00); i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x00);
} }
else { else {
// Show major ISTEP on LED bank // Show major ISTEP on LED bank
...@@ -428,7 +439,7 @@ static void display_post_code(uint16_t post_code) ...@@ -428,7 +439,7 @@ static void display_post_code(uint16_t post_code)
} }
set_led_bank_display(led_post_code); set_led_bank_display(led_post_code);
i2c_write_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x80 | host_status_led_post_code); i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x80 | host_status_led_post_code);
} }
} }
...@@ -440,6 +451,10 @@ static void gpio_init(void) ...@@ -440,6 +451,10 @@ static void gpio_init(void)
// Set up alphanumeric display / power LED // Set up alphanumeric display / power LED
gpio2_out_write((' ' << 24) | (' ' << 16) | (' ' << 8) | ' '); gpio2_out_write((' ' << 24) | (' ' << 16) | (' ' << 8) | ' ');
// Set up and turn off power LED
gpio1_out_write(gpio1_out_read() & ~(0x01 << POWER_LED_OUT_GPIO));
gpio1_oe_write(gpio1_oe_read() | (0x01 << POWER_LED_OUT_GPIO));
} }
static void set_lpc_slave_irq_enable(uint8_t enabled) static void set_lpc_slave_irq_enable(uint8_t enabled)
...@@ -2284,7 +2299,7 @@ void power_off_chassis(int has_lock) ...@@ -2284,7 +2299,7 @@ void power_off_chassis(int has_lock)
} }
// Power off host via platform FPGA commands // Power off host via platform FPGA commands
i2c_write_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_MFR_OVR, 0x00); i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_MFR_OVR, 0x00);
run_post_shutdown_bmc_peripheral_teardown(); run_post_shutdown_bmc_peripheral_teardown();
...@@ -2317,7 +2332,7 @@ int power_on_chassis(int has_lock) ...@@ -2317,7 +2332,7 @@ int power_on_chassis(int has_lock)
display_character('0' + 2 + host_power_status, 0); // STATUS CODE display_character('0' + 2 + host_power_status, 0); // STATUS CODE
// Verify communication with platform control FPGA // Verify communication with platform control FPGA
platform_fpga_identifier[0] = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0c, NULL); platform_fpga_identifier[0] = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0c, NULL);
if (platform_fpga_identifier[0] == 0xff) if (platform_fpga_identifier[0] == 0xff)
{ {
host_power_status = HOST_POWER_STATUS_OFFLINE; host_power_status = HOST_POWER_STATUS_OFFLINE;
...@@ -2328,9 +2343,9 @@ int power_on_chassis(int has_lock) ...@@ -2328,9 +2343,9 @@ int power_on_chassis(int has_lock)
} }
return -1; return -1;
} }
platform_fpga_identifier[1] = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0d, NULL); platform_fpga_identifier[1] = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0d, NULL);
platform_fpga_identifier[2] = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0e, NULL); platform_fpga_identifier[2] = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0e, NULL);
platform_fpga_identifier[3] = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0f, NULL); platform_fpga_identifier[3] = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, 0x0f, NULL);
if ((platform_fpga_identifier[0] != 0x52) || (platform_fpga_identifier[1] != 0x43) || (platform_fpga_identifier[2] != 0x53) || if ((platform_fpga_identifier[0] != 0x52) || (platform_fpga_identifier[1] != 0x43) || (platform_fpga_identifier[2] != 0x53) ||
(platform_fpga_identifier[3] != 0x20)) (platform_fpga_identifier[3] != 0x20))
{ {
...@@ -2349,9 +2364,9 @@ int power_on_chassis(int has_lock) ...@@ -2349,9 +2364,9 @@ int power_on_chassis(int has_lock)
// Power on host via platform FPGA commands // Power on host via platform FPGA commands
KESTREL_LOG("Commanding chassis power ON..."); KESTREL_LOG("Commanding chassis power ON...");
i2c_write_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_MFR_OVR, 0x01); i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_MFR_OVR, 0x01);
platform_power_on_timeout_counter = 0; platform_power_on_timeout_counter = 0;
byte = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STATUS, &i2c_read_retcode); byte = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STATUS, &i2c_read_retcode);
while (i2c_read_retcode || (((byte)&0x03) != 0x03)) while (i2c_read_retcode || (((byte)&0x03) != 0x03))
{ {
if (platform_power_on_timeout_counter > 20000) if (platform_power_on_timeout_counter > 20000)
...@@ -2365,7 +2380,7 @@ int power_on_chassis(int has_lock) ...@@ -2365,7 +2380,7 @@ int power_on_chassis(int has_lock)
} }
usleep(100); usleep(100);
platform_power_on_timeout_counter++; platform_power_on_timeout_counter++;
byte = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STATUS, &i2c_read_retcode); byte = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STATUS, &i2c_read_retcode);
} }
if (i2c_read_retcode) if (i2c_read_retcode)
{ {
...@@ -2450,7 +2465,7 @@ void print_chassis_status(void) ...@@ -2450,7 +2465,7 @@ void print_chassis_status(void)
int i2c_read_retcode; int i2c_read_retcode;
uint8_t byte; uint8_t byte;
byte = i2c_read_register_byte((uint8_t *)I2CMASTER4_BASE, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STATUS, &i2c_read_retcode); byte = i2c_read_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STATUS, &i2c_read_retcode);
if (i2c_read_retcode) if (i2c_read_retcode)
{ {
KESTREL_LOG("Unable to communicate with platform control FPGA!"); KESTREL_LOG("Unable to communicate with platform control FPGA!");
...@@ -3603,7 +3618,7 @@ int kestrel_init(void) ...@@ -3603,7 +3618,7 @@ int kestrel_init(void)
initialize_i2c_master(g_cpu_info[i].i2c_master, g_cpu_info[i].i2c_frequency); initialize_i2c_master(g_cpu_info[i].i2c_master, g_cpu_info[i].i2c_frequency);
} }
// initialize_i2c_master((uint8_t*)I2CMASTER3_BASE, 100000); // initialize_i2c_master((uint8_t*)I2CMASTER3_BASE, 100000);
initialize_i2c_master((uint8_t *)I2CMASTER4_BASE, 100000); initialize_i2c_master((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, 100000);
#ifdef SIMPLEPWM_BASE #ifdef SIMPLEPWM_BASE
initialize_pwm_controller((uint8_t*)SIMPLEPWM_BASE); initialize_pwm_controller((uint8_t*)SIMPLEPWM_BASE);
......
...@@ -14,16 +14,22 @@ ...@@ -14,16 +14,22 @@
#if (WITH_ZEPHYR) #if (WITH_ZEPHYR)
#define SW0_NODE DT_ALIAS(sw0) #define SW0_NODE DT_ALIAS(sw0)
#define SW0_HOG_NODE DT_ALIAS(swhog0)
#if DT_NODE_HAS_STATUS(SW0_NODE, okay) #if DT_NODE_HAS_STATUS(SW0_NODE, okay)
#define KESTREL_HOST_POWER_BUTTON_GPIO DT_GPIO_LABEL(SW0_NODE, gpios) #define KESTREL_HOST_POWER_BUTTON_GPIO DT_GPIO_LABEL(SW0_NODE, gpios)
#define KESTREL_HOST_POWER_BUTTON_PIN DT_GPIO_PIN(SW0_NODE, gpios) #define KESTREL_HOST_POWER_BUTTON_PIN DT_GPIO_PIN(SW0_NODE, gpios)
#define KESTREL_HOST_POWER_BUTTON_HOG_GPIO DT_GPIO_LABEL(SW0_HOG_NODE, gpios)
#define KESTREL_HOST_POWER_BUTTON_HOG_PIN DT_GPIO_PIN(SW0_HOG_NODE, gpios)
#else #else
#error "No power button defined in device tree" #error "No power button defined in device tree"
#endif #endif
#define SW1_NODE DT_ALIAS(sw1) #define SW1_NODE DT_ALIAS(sw1)
#define SW1_HOG_NODE DT_ALIAS(swhog1)
#if DT_NODE_HAS_STATUS(SW1_NODE, okay) #if DT_NODE_HAS_STATUS(SW1_NODE, okay)
#define KESTREL_HOST_RESET_BUTTON_GPIO DT_GPIO_LABEL(SW1_NODE, gpios) #define KESTREL_HOST_RESET_BUTTON_GPIO DT_GPIO_LABEL(SW1_NODE, gpios)
#define KESTREL_HOST_RESET_BUTTON_PIN DT_GPIO_PIN(SW1_NODE, gpios) #define KESTREL_HOST_RESET_BUTTON_PIN DT_GPIO_PIN(SW1_NODE, gpios)
#define KESTREL_HOST_RESET_BUTTON_HOG_GPIO DT_GPIO_LABEL(SW1_HOG_NODE, gpios)
#define KESTREL_HOST_RESET_BUTTON_HOG_PIN DT_GPIO_PIN(SW1_HOG_NODE, gpios)
#else #else
#error "No reset button defined in device tree" #error "No reset button defined in device tree"
#endif #endif
......
...@@ -163,6 +163,18 @@ static int configure_gpios(void) ...@@ -163,6 +163,18 @@ static int configure_gpios(void)
retcode = 0; retcode = 0;
// Set up power button // Set up power button
button = device_get_binding(KESTREL_HOST_POWER_BUTTON_HOG_GPIO);
if (button == NULL) {
printk("[ERROR] Unable to locate host power button hog on node %s\n", KESTREL_HOST_POWER_BUTTON_HOG_GPIO);
retcode = -1;
}
else {
ret = gpio_pin_configure(button, KESTREL_HOST_POWER_BUTTON_HOG_PIN, GPIO_OUTPUT_HIGH);
if (ret != 0) {
printk("[ERROR] failed to configure hog on %s pin %d (returned %d)\n", KESTREL_HOST_POWER_BUTTON_HOG_GPIO, KESTREL_HOST_POWER_BUTTON_HOG_PIN, ret);
retcode = -1;
}
}
button = device_get_binding(KESTREL_HOST_POWER_BUTTON_GPIO); button = device_get_binding(KESTREL_HOST_POWER_BUTTON_GPIO);
if (button == NULL) { if (button == NULL) {
printk("[ERROR] Unable to locate host power button on node %s\n", KESTREL_HOST_POWER_BUTTON_GPIO); printk("[ERROR] Unable to locate host power button on node %s\n", KESTREL_HOST_POWER_BUTTON_GPIO);
...@@ -181,6 +193,18 @@ static int configure_gpios(void) ...@@ -181,6 +193,18 @@ static int configure_gpios(void)
} }
// Set up reset button // Set up reset button
button = device_get_binding(KESTREL_HOST_RESET_BUTTON_HOG_GPIO);
if (button == NULL) {
printk("[ERROR] Unable to locate host reset button hog on node %s\n", KESTREL_HOST_RESET_BUTTON_HOG_GPIO);
retcode = -1;
}
else {
ret = gpio_pin_configure(button, KESTREL_HOST_RESET_BUTTON_HOG_PIN, GPIO_OUTPUT_HIGH);
if (ret != 0) {
printk("[ERROR] failed to configure hog on %s pin %d (returned %d)\n", KESTREL_HOST_RESET_BUTTON_HOG_GPIO, KESTREL_HOST_RESET_BUTTON_HOG_PIN, ret);
retcode = -1;
}
}
button = device_get_binding(KESTREL_HOST_RESET_BUTTON_GPIO); button = device_get_binding(KESTREL_HOST_RESET_BUTTON_GPIO);
if (button == NULL) { if (button == NULL) {
printk("[ERROR] Unable to locate host reset button on node %s\n", KESTREL_HOST_RESET_BUTTON_GPIO); printk("[ERROR] Unable to locate host reset button on node %s\n", KESTREL_HOST_RESET_BUTTON_GPIO);
......
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