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Zephyr Firmware
Commit 13cbede0 authored by Raptor Engineering Development Team's avatar Raptor Engineering Development Team
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Don't unconditionally enable advanced SPI Flash features 

Fast read and quad SPI are not supported by all Flash
devices / board wiring schemes.  Only enable them if
the detected and configured device supports them.
parent 7e5e8817
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Showing with 24 additions and 21 deletions
kestrel/src/kestrel.c
View file @ 13cbede0
......@@ -3151,7 +3151,7 @@ static void console_service(void)
#endif
#if (WITH_SPI)
static int tercel_spi_flash_init(uintptr_t spi_ctl_cfgaddr, uintptr_t spi_ctl_baseaddr, int clock_divisor, int enable_4ba)
static int tercel_spi_flash_init(uintptr_t spi_ctl_cfgaddr, uintptr_t spi_ctl_baseaddr, int clock_divisor, int qspi_capable, int enable_4ba)
{
int i;
uint32_t dword;
......@@ -3203,6 +3203,19 @@ static int tercel_spi_flash_init(uintptr_t spi_ctl_cfgaddr, uintptr_t spi_ctl_ba
dword |= TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_MASK << TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_SHIFT;
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
// Set SPI fast read dummy cycles to
// MICRON_N25Q_SPI_FAST_READ_DUMMY_CLOCK_CYCLES
dword = read_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1);
dword &= ~(TERCEL_SPI_PHY_DUMMY_CYCLES_MASK << TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT);
dword |= ((MICRON_N25Q_SPI_FAST_READ_DUMMY_CLOCK_CYCLES & TERCEL_SPI_PHY_DUMMY_CYCLES_MASK) << TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
// Enable SPI fast read functionality
dword = read_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1);
dword &= ~(TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK << TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT);
dword |= ((1 & TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK) << TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
break;
}
}
......@@ -3224,19 +3237,6 @@ static int tercel_spi_flash_init(uintptr_t spi_ctl_cfgaddr, uintptr_t spi_ctl_ba
dword |= ((10000 & TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_MASK) << TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_FLASH_CFG4, dword);
// Set SPI fast read dummy cycles to
// MICRON_N25Q_SPI_FAST_READ_DUMMY_CLOCK_CYCLES
dword = read_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1);
dword &= ~(TERCEL_SPI_PHY_DUMMY_CYCLES_MASK << TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT);
dword |= ((MICRON_N25Q_SPI_FAST_READ_DUMMY_CLOCK_CYCLES & TERCEL_SPI_PHY_DUMMY_CYCLES_MASK) << TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
// Enable SPI fast read functionality
dword = read_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1);
dword &= ~(TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK << TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT);
dword |= ((1 & TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK) << TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
if (enable_4ba)
{
// Set SPI controller to 4BA mode
......@@ -3247,11 +3247,14 @@ static int tercel_spi_flash_init(uintptr_t spi_ctl_cfgaddr, uintptr_t spi_ctl_ba
}
#if (ALLOW_SPI_QUAD_MODE)
// Set SPI controller to QSPI mode
dword = read_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1);
dword &= ~(TERCEL_SPI_PHY_IO_TYPE_MASK << TERCEL_SPI_PHY_IO_TYPE_SHIFT);
dword |= ((TERCEL_SPI_PHY_IO_TYPE_QUAD & TERCEL_SPI_PHY_IO_TYPE_MASK) << TERCEL_SPI_PHY_IO_TYPE_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
if (qspi_capable)
{
// Set SPI controller to QSPI mode
dword = read_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1);
dword &= ~(TERCEL_SPI_PHY_IO_TYPE_MASK << TERCEL_SPI_PHY_IO_TYPE_SHIFT);
dword |= ((TERCEL_SPI_PHY_IO_TYPE_QUAD & TERCEL_SPI_PHY_IO_TYPE_MASK) << TERCEL_SPI_PHY_IO_TYPE_SHIFT);
write_tercel_register(spi_ctl_cfgaddr, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
}
#endif
// Set SPI clock cycle divider
......@@ -3524,7 +3527,7 @@ int kestrel_init(void)
#if (WITH_SPI)
// Initialize BMC Flash controller
tercel_spi_flash_init(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE, 1, 0);
tercel_spi_flash_init(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE, 1, 0, 0);
// Detect and print attached host SPI Flash ID
KESTREL_LOG("Host SPI flash ID: 0x%08x", read_host_spi_flash_id(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE));
......@@ -3533,7 +3536,7 @@ int kestrel_init(void)
configure_flash_device(BMCSPIFLASHCFG_BASE, BMCSPIFLASH_BASE);
// Initialize host Flash controller
tercel_spi_flash_init(HOSTSPIFLASHCFG_BASE, HOSTSPIFLASH_BASE, 5, 1);
tercel_spi_flash_init(HOSTSPIFLASHCFG_BASE, HOSTSPIFLASH_BASE, 5, 1, 1);
// Detect and print attached host SPI Flash ID
KESTREL_LOG("Host SPI flash ID: 0x%08x", read_host_spi_flash_id(HOSTSPIFLASHCFG_BASE, HOSTSPIFLASH_BASE));
......
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