Display IPL status on host platform LEDs

This adds functionality currently present in the ASpeed
BMC firmware stack.
parent 2bbafe9b
Pipeline #269 passed with stage
in 19 seconds
......@@ -100,6 +100,7 @@
// General RCS platform registers
#define HOST_PLATFORM_FPGA_I2C_REG_STATUS 0x7
#define HOST_PLATFORM_FPGA_I2C_REG_STA_LED 0x10
#define HOST_PLATFORM_FPGA_I2C_REG_MFR_OVR 0x33
// Host platform configuration
......@@ -337,6 +338,7 @@ static void reboot(void)
ctrl_reset_write(1);
}
#if (PLATFORM_ARCTIC_TERN)
static void msleep(int ms)
{
uint64_t timestamp = uptime_counter_ms;
......@@ -350,6 +352,7 @@ static void msleep(int ms)
}
}
}
#endif
#if (PLATFORM_VERSA_ECP5)
static void display_character(char character, int dp)
......@@ -575,6 +578,114 @@ static void sparrowhawk_base_platform_init(void)
}
#endif
static void display_post_code(uint16_t post_code)
{
uint8_t host_status_led_post_code;
uint8_t major_istep = ((post_code >> 8) & 0xff);
uint8_t led_post_code = (((post_code >> 8) & 0xf) << 4) | (post_code & 0xf);
if (post_code == 0xfefe)
{
// IPL complete!
set_led_bank_display(0);
i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x00);
}
else if (post_code == 0x0)
{
// System offline
set_led_bank_display(0);
i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED, 0x00);
}
else
{
// Show major ISTEP on LED bank
// On Talos we only have three LEDs plus a fourth indicator modification bit, but the major ISTEPs range from 2 to 21
// Try to condense that down to something more readily displayable
switch (major_istep)
{
case 2:
host_status_led_post_code = 1;
break;
case 3:
host_status_led_post_code = 1;
break;
case 4:
host_status_led_post_code = 2;
break;
case 5:
host_status_led_post_code = 2;
break;
case 6:
host_status_led_post_code = 3;
break;
case 7:
host_status_led_post_code = 3;
break;
case 8:
host_status_led_post_code = 4;
break;
case 9:
host_status_led_post_code = 4;
break;
case 10:
host_status_led_post_code = 5;
break;
case 11:
host_status_led_post_code = 5;
break;
case 12:
host_status_led_post_code = 6;
break;
case 13:
host_status_led_post_code = 6;
break;
case 14:
host_status_led_post_code = 7;
break;
case 15:
host_status_led_post_code = 7;
break;
case 16:
host_status_led_post_code = 9;
break;
case 17:
host_status_led_post_code = 9;
break;
case 18:
host_status_led_post_code = 10;
break;
case 19:
host_status_led_post_code = 10;
break;
case 20:
host_status_led_post_code = 11;
break;
case 21:
host_status_led_post_code = 11;
break;
case 22:
host_status_led_post_code = 12;
break;
case 23:
host_status_led_post_code = 12;
break;
default:
host_status_led_post_code = 0;
}
if (PLATFORM_ARCTIC_TERN)
{
set_led_bank_display(post_code);
}
else
{
set_led_bank_display(led_post_code);
}
i2c_write_register_byte((uint8_t *)P9PS_I2C_MASTER_BASE_ADDR, HOST_PLATFORM_FPGA_I2C_ADDRESS, HOST_PLATFORM_FPGA_I2C_REG_STA_LED,
0x80 | host_status_led_post_code);
}
}
#ifdef GPIO1_INTERRUPT
static void set_discrete_gpio_irq_enable(uint8_t enable, uint32_t enabled_pins)
{
......@@ -1726,7 +1837,7 @@ static void run_pre_ipl_bmc_peripheral_setup(void)
// Reset POST codes and display
post_code_high = 0;
post_code_low = 0;
set_led_bank_display(0x0000);
display_post_code(0x0);
// Deactivate interrupts on entering critical section
irq_setie(0);
......@@ -1865,7 +1976,7 @@ static void run_post_shutdown_bmc_peripheral_teardown(void)
// Reset POST codes and display
post_code_high = 0;
post_code_low = 0;
set_led_bank_display(0x0000);
display_post_code(0x0);
}
static int apply_avsbus_workarounds_cpu(const cpu_info_t *cpu)
......@@ -2465,7 +2576,7 @@ static void host_background_service_task_event_loop(void)
else if (address == 0x82)
{
post_code_low = post_code;
set_led_bank_display(((post_code_high & 0xff) << 8) | (post_code_low & 0xff));
display_post_code(((post_code_high & 0xff) << 8) | (post_code_low & 0xff));
if (enable_post_code_console_output)
{
......
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