Enable Flash writes by default

Automatically soft-enable Flash writes when Flash writes
allowed by build configuration.

Don't attempt to set QSPI control bits when QSPI mode is
disabled.

main.c

@@ -91,7 +91,7 @@
 #define ENABLE_LPC_FW_CYCLE_IRQ_HANDLER 1 // Set to 1 to enable LPC master transfer interrupts to the BMC soft core
 #define ENABLE_LPC_FW_CYCLE_DMA         1 // Set to 1 to allow the LPC master to DMA data to/from the Wishbone bus (not compatible with direct SPI access)
 #define ALLOW_SPI_QUAD_MODE             0 // Set to 1 to allow quad-mode SPI transfers if the hardware supports them
-#define ALLOW_FLASH_WRITES              0 // Allow writes to PNOR Flash device
+#define ALLOW_FLASH_WRITES              1 // Allow writes to PNOR Flash device
 
 // Debug knobs
 #define DEBUG_HOST_SPI_FLASH_READ               0 // Set to 1 to enable verbose logging of SPI flash read process
@@ -176,7 +176,11 @@ uint8_t post_code_high = 0;
 uint8_t post_code_low = 0;
 
 // Global configuration
+#if (ALLOW_FLASH_WRITES)
+static uint8_t allow_flash_write = 1;
+#else
 static uint8_t allow_flash_write = 0;
+#endif
 static uint8_t enable_post_code_console_output = 0;
 
 typedef struct
@@ -3152,11 +3156,13 @@ static int host_spi_flash_init(void)
             dword |= (MICRON_N25Q_SPI_3BA_SPI_PAGE_PROGRAM_CMD & TERCEL_SPI_3BA_SPI_CMD_MASK) << TERCEL_SPI_3BA_SPI_CMD_SHIFT;
             write_tercel_register(HOSTSPIFLASHCFG_BASE, TERCEL_SPI_REG_SYS_FLASH_CFG3, dword);
 
+#if (ALLOW_SPI_QUAD_MODE)
             // Enable extended QSPI read/write operations
             dword = read_tercel_register(HOSTSPIFLASHCFG_BASE, TERCEL_SPI_REG_SYS_PHY_CFG1);
             dword |= TERCEL_SPI_PHY_QSPI_EXT_READ_EN_MASK << TERCEL_SPI_PHY_QSPI_EXT_READ_EN_SHIFT;
             dword |= TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_MASK << TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_SHIFT;
             write_tercel_register(HOSTSPIFLASHCFG_BASE, TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
+#endif
 
             break;
         }