- 01 Aug, 2020 2 commits
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Raptor Engineering Development Team authored
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Raptor Engineering Development Team authored
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- 21 Jul, 2020 3 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 20 Jul, 2020 7 commits
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enjoy-digital authored
Fix Vivado crash when using 1:1 wishbone.Converter
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enjoy-digital authored
wire up missing register bits.
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enjoy-digital authored
interconnect/csr_bus: fix paged access warning
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Ilia Sergachev authored
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Jędrzej Boczar authored
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at: https://github.com/antmicro/litex-buildenv/commit/cc003bef3ac1407f9788ec8b7cc52d5981f8364a and litex bumped to 4a18b828, with options: CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net The only difference in Verilog is that we avoid creating new Interface and doing `new_interface.connect(interface)`, so this shouldn't make any difference, but this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
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Florent Kermarrec authored
software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz.
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Florent Kermarrec authored
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value). - Allow clk_divider down to 2. - improve test errors reporting with hex() on AssertEqual.
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- 18 Jul, 2020 1 commit
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bunnie authored
Not sure how they went missing...but just noticed them.
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- 17 Jul, 2020 4 commits
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- 16 Jul, 2020 6 commits
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Florent Kermarrec authored
For example: { "Image": "0x40000000", "bootargs": { "r1": "0x12345678", } } will copy Image to 0x40000000 and set r1 to 0x12345678. By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so: { "Image": "0x40000000", "rootfs.cpio": "0x40800000", "rv32.dtb": "0x41000000", "emulator.bin": "0x41100000", } is equivalent to: { "Image": "0x40000000", "rootfs.cpio": "0x40800000", "rv32.dtb": "0x41000000", "emulator.bin": "0x41100000", "bootargs": { "r1": "0x00000000", "r2": "0x00000000", "r3": "0x00000000", "addr": "0x00000000", } }
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enjoy-digital authored
Add AXILiteDownConverter
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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enjoy-digital authored
Add AXILite components: AXILiteSRAM and AXILite2CSR
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Jędrzej Boczar authored
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- 15 Jul, 2020 8 commits
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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enjoy-digital authored
symbiflow: changed toolchain command names in Makefile
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Jędrzej Boczar authored
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Alessandro Comodi authored
Signed-off-by:
Alessandro Comodi <acomodi@antmicro.com>
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Jędrzej Boczar authored
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Jędrzej Boczar authored
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- 14 Jul, 2020 1 commit
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Jędrzej Boczar authored
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- 13 Jul, 2020 1 commit
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Florent Kermarrec authored
build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. Using fast-read as default prevent loading the .bit via JTAG (see #589).
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- 11 Jul, 2020 3 commits
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Florent Kermarrec authored
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enjoy-digital authored
trellis: Add option to select SPI mode.
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Owen Kirby authored
This allows a significant speedup when booting large bitstreams on ECP5 boards that support dual or quad SPI operation.
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- 10 Jul, 2020 4 commits
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enjoy-digital authored
mor1kx: Do not generate the ror instruction
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Florent Kermarrec authored
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Mateusz Holenko authored
The mor1kx core does not support `l.ror` instruction by default, but gcc/clang flags allowed the compiler to generate it.
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Florent Kermarrec authored
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