Fix Vivado crash when using 1:1 wishbone.Converter

wire up missing register bits.

interconnect/csr_bus: fix paged access warning

Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
https://github.com/antmicro/litex-buildenv/commit/cc003bef3ac1407f9788ec8b7cc52d5981f8364a
and litex bumped to 4a18b828,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).

software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz.

- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.

Not sure how they went missing...but just noticed them.

For example:
{
	"Image":  "0x40000000",
	"bootargs": {
		"r1":  "0x12345678",
	}
}

will copy Image to 0x40000000 and set r1 to 0x12345678.

By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
}

is equivalent to:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
	"bootargs": {
		"r1":   "0x00000000",
		"r2":   "0x00000000",
		"r3":   "0x00000000",
		"addr": "0x00000000",
	}
}

Add AXILiteDownConverter

Add AXILite components: AXILiteSRAM and AXILite2CSR

symbiflow: changed toolchain command names in Makefile

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read.

Using fast-read as default prevent loading the .bit via JTAG (see #589).

trellis: Add option to select SPI mode.

This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.

mor1kx: Do not generate the ror instruction

The mor1kx core does not support `l.ror` instruction
by default, but gcc/clang flags allowed the
compiler to generate it.