also delay boot at kermit transfer by ~1s to allow the program to resume listening to the console

Note that the intigration might want to be improved a bit.

however none of the bits are hooked up.

note so really weird stuff is going on, simply commenting out/uncommenting
an _early_dbg_abi call can change the behavior of print code invoked *before* it. (and interrupts are disabled, so it should all be polling)

it seems injecting the waits has cause it to work... which means there is still a bug

There is a conflict between the LiteX way of doing things and the POWER
way of handling interrupt tables.  LiteX expects to be able to put a ROM
at address 0 and load an application into RAM at a higher address; POWER
is architected to jump to exception handlers at 0x100...0x1000.

As a result of this, we have taken the approach of placing generic exception
handler entry / exit routines into ROM, and reserving a single pointer in
SRAM to determine the C ISR handler location.  If no application is loaded,
this pointer is set to the BIOS ROM ISR.  When an application loads, before
reenabling interrupts, it needs to set __rom_isr_address to the address of
the application's ISR, otherwise the BIOS ROM ISR will continue to be used.

Tested to operate with the built-in UART in IRQ mode, both in BIOS and in
loaded RAM application.

This reverts commit f3dda2b1.

Fix Vivado crash when using 1:1 wishbone.Converter

wire up missing register bits.

interconnect/csr_bus: fix paged access warning

Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
https://github.com/antmicro/litex-buildenv/commit/cc003bef3ac1407f9788ec8b7cc52d5981f8364a
and litex bumped to 4a18b828,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).

software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz.

- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.

Not sure how they went missing...but just noticed them.