De10lite support

Extend generated headers & csv

For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.

software/libbase: memcpy: simple, arch-width agnostic implementation

Remove optimizations targeted specifically at rv32 architecture,
allowing memcpy to work on all word sizes.

Since this is "only" the BIOS, it is also arguably better to
optimize for size rather than performance, given that control
will be quickly handed over to some other program being loaded.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

fix signed char type to be explicitly signed

needed for some third party libraries to compile

Fix interrupt_name in soc_core/add_interrupt

Add support for Terasic DE2-115 and Terasic DE1-SoC boards

update stdint.h to include c99 types

See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=502&PartNo=1
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>

See https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=836
for board details.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>

Miscellaneous cleanup patches

Factor out code appearing in both branches of an if/else.

Allow ethernet to work when sys_clk_freq != 100MHz

litex/boards/targets: don't use tab for indentation

Fix pep8 E101 "indentation contains mixed spaces and tab" error.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>

boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it)

Experimental Support for 64-bit RocketChip

FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS

Simulate a Rocket-based 64-bit LiteX SoC with the following command:

  litex/tools/litex_sim.py [--with-sdram] --cpu-type=rocket

NOTE: Synthesizes to FPGA and passes timing at 50MHz on nexys4ddr
(with vivado) and ecp5versa (with yosys/trellis/nextpnr), but at
this time does not yet properly initialize physical on-board DRAM.
On ecp5versa, using '--with-ethernet', up to 97% of the available
TRELLIS_SLICE capacity is utilized.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>