tools/litex_sim: fix default endianness for mem_init

Initializing ROM and/or RAM content requires knowing the CPU
endianness before the SimSoC->SoCSDRAM->SoCCore constructor
sequence is invoked (before the SoC's self.cpu.endianness
could be accessed). Given that the majority of supported CPU
models use "little", set it as the new default, and override
only for the two models that use "big" endianness.

cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants

bios: Fix build when ethphy is present but ethmac is not.

While testing my Ethernet DMA, I renamed the `ethmac` module to `ethmac_dma` so that it wouldn't be used from the BIOS, but I got an undefined reference to `eth_init` because `bios.c` checks different CSR defines than the code that defines `eth_init`.

boards/arty : Add directly connected spi clk pin 

Imported from LiteICLink. PRBS can be useful for different purposes, so is
better integrated in LiteX.

When running OS with LiteX and when LiteXTerm is use, we want to be able to
send CTRl-C to the OS. Ensure a specific sequence is sent to close the terminal.

In most of the case, execution speed is already fast enough with -O0 and
with complex design -O0 is a lost faster to compile than -O3. In the future
we could add a switch to choose which optimization we want.

De10lite support

Extend generated headers & csv

For some FPGAs (e.g. MAX10) .rbf file cannot be generated.
Add possibility to turn off that feature for those chips.

software/libbase: memcpy: simple, arch-width agnostic implementation