Use 0x43/0xc3 for USB bridge magic packet

When we get an error with errno 13, it means that the user doesn't
have access to the USB device.  Rather than silently eating this
error and returning -1, print out a message to aid in debugging.
Signed-off-by: Sean Cross <sean@xobs.io>

The previous value -- 0xc0 -- is used by Windows all the time to query
special descriptors.  This was causing a conflict when using the USB
bridge on a Windows device.

Change the magic packet from "Vendor: Device" queries to "Vendor:
Other" by setting the bottom two bits.
Signed-off-by: Sean Cross <sean@xobs.io>

boards/nexys4ddr: ethernet support fix-up

Commit 5f6e7874 added ethernet support, let's now also expose it via
the "--with-ethernet" command line argument.

This could be useful in specific case were we don't have a wishbone master
but just want to have a csr bus and allow the user to define it.

/!\ Since there is no arbitration on between the CSR masters, use this with
precaution /!\

Cordic is useful for DSP cores but not as a Soc building block.

axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has  proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.

soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy

For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.

Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.

The previous way to define interrupt is still valid, but using add_interrupt
method will ease maintenance

The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.

Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.

soc/integration/cpu_interface: more arch-specific address size fixes

When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.

Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.

Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

Most of the targets can now generate an abritrary sys_clk_freq from onboard XO.

example json file (serialboot.json):
{
	"binaries/Image":         "0xc0000000",
	"binaries/rootfs.cpio":   "0xc2000000",
	"binaries/rv32.dtb":      "0xc3000000",
	"emulator/emulator.bin":  "0x20000000"
}

example command:
lxterm --images=serialboot.json /dev/ttyUSBX

vexriscv: Fix some floating signals