This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.

mor1kx: Do not generate the ror instruction

The mor1kx core does not support `l.ror` instruction
by default, but gcc/clang flags allowed the
compiler to generate it.

cpu: add a few missing GCC toolchains

This names are used by Arch Linux for eg.
Signed-off-by: Filipe Laíns <lains@archlinux.org>

Memtest/memspeed improvements

Otherwise we have at least an extra addition in the loop
which squews the result compared to the read loop.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Just create a local clk_domain from clk signal.

The move to libbase reverted the type of the pointer
from long to int.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

In a couple of places, memtest uses %x to print a pointer which
is illegal (and could be problematic on 64-bit). Use %p instead.

Additionally, use %ld when printing longs
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

liblitesdcard/sdcard: adjust card-ready timeout

Testing on nexys4ddr and rocket, approximately 12 iterations of the
timeout loop (using `busy_wait(1)`) are needed to receive a "ready"
response from the SDcard, assuming a "warm" reset where the card has
already been previously initialized.

If the SDcard is ejected and re-inserted, or if the board is "cold-reset"
(e.g., reprogrammed via openocd vs. a simple push of the reset button),
it takes approximately 450 iterations before the SDCard responds with a
"ready" message.

In either case, a timeout of 10 is insufficient. This patch increases
the busy-wait to 10, and the timeout loop counter to 128, which should
cover most cases.

Additionally, make a few minor cosmetic improvements.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

Was incorrectly triggered with csr_data_width=32.

Minor sdcard fixes

litelitesdcard/sdcard: remove wait workaround and replace remove SDCARD_MULTIPLE_BLOCK_SUPPORT define (replace it with SDCARD_CMD23_SUPPORT).

integration/soc/etherbone: always run ethcore in eth_tx clock domain and remove clock_domain parameter.

This avoid issues when sys_clk_freq < eth_tx clock like sys_clk_freq < 125MHz with 1Gbps link.

i2s: Fix the incorrect TX fifo almost empty offset