Commit e4dcf33d authored by Tim 'mithro' Ansell's avatar Tim 'mithro' Ansell

Move llvm to https://

parent e1f47f18
......@@ -6,7 +6,7 @@
url =
[submodule "litex/soc/software/compiler_rt"]
path = litex/soc/software/compiler_rt
url =
url =
[submodule "litex/soc/cores/cpu/picorv32/verilog"]
path = litex/soc/cores/cpu/picorv32/verilog
url =
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