Commit e46d287b authored by Florent Kermarrec's avatar Florent Kermarrec

targets/ulx3s: use CAS latency of 3 to be compatible with production boards

parent 113f7f40
......@@ -59,7 +59,7 @@ class BaseSoC(SoCSDRAM):
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3)
sdram_module = MT48LC16M16(sys_clk_freq, "1:1")
self.register_sdram(self.sdrphy,
sdram_module.geom_settings,
......
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