From cf369c437c657eae0aa72ad5524ef37d9739f172 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 24 May 2019 09:37:33 +0200
Subject: [PATCH] boards/targets: revert default sys_clk_freq on
nexys4ddr/versa_ecp5 (but add parameter to configure it)
---
litex/boards/targets/nexys4ddr.py | 6 ++++--
litex/boards/targets/versa_ecp5.py | 6 ++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py
index 77fcb5a6..c847d2b4 100755
--- a/litex/boards/targets/nexys4ddr.py
+++ b/litex/boards/targets/nexys4ddr.py
@@ -47,7 +47,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(50e6), **kwargs):
+ def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = nexys4ddr.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
@@ -102,12 +102,14 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
builder_args(parser)
soc_sdram_args(parser)
+ parser.add_argument("--sys-clk-freq", default=75e6,
+ help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
- soc = cls(**soc_sdram_argdict(args))
+ soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 035a32a5..c1ab6756 100755
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -73,7 +73,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
- def __init__(self, sys_clk_freq=int(50e6), toolchain="diamond", **kwargs):
+ def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000,
@@ -130,12 +130,14 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser)
soc_sdram_args(parser)
+ parser.add_argument("--sys-clk-freq", default=75e6,
+ help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
- soc = cls(toolchain=args.toolchain, **soc_sdram_argdict(args))
+ soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
--
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