From a49d170a6d03d6078f973566575b097eeebbacb9 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 10 May 2019 15:46:22 +0200
Subject: [PATCH] soc/integration/soc_sdram: simplify/fix main_ram_size
computation using new databits value of the phy
---
litex/soc/integration/soc_sdram.py | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 64b218ad..c9c09fab 100644
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -62,13 +62,10 @@ class SoCSDRAM(SoCCore):
self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, **kwargs)
- dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
- sdram_width = phy.settings.dfi_databits//dfi_databits_divisor
+ # TODO: modify mem_map to allow larger memories.
main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits +
- geom_settings.colbits)*sdram_width//8
-
- # TODO: modify mem_map to allow larger memories.
+ geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 256*1024*1024)
self.add_constant("L2_SIZE", self.l2_size)
--
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