Allow the build to set the reset address, and default it to 0x40000000

Iit would be nice to route this all the way up to versa_ecp5.py,
however I've spent too long fighting with litex,
that will have to be resolved later.

litex/soc/cores/cpu/microwatt/core.py

@@ -138,6 +138,7 @@ class Microwatt(CPU):
     linker_output_format = "elf64-powerpcle"
     nop                  = "nop"
     io_regions           = {0xc0000000: 0x10000000} # origin, length
+    reset_address        = 0
 
     @property
     def mem_map(self):
@@ -159,7 +160,7 @@ class Microwatt(CPU):
         flags += "-D__microwatt__ "
         return flags
 
-    def __init__(self, platform, variant="standard"):
+    def __init__(self, platform, variant="standard", reset_address='''x"0000000040000000"'''):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
@@ -171,6 +172,7 @@ class Microwatt(CPU):
         self.core_ext_irq = Signal()
 
         # # #
+        self.reset_address = reset_address
 
         self.cpu_params = dict(
             # Clock / Reset
@@ -231,8 +233,7 @@ class Microwatt(CPU):
             core_irq_out = self.core_ext_irq,
             int_level_in = self.interrupt)
 
-    @staticmethod
-    def add_sources(platform, use_ghdl_yosys_plugin=False):
+    def add_sources(self, platform, use_ghdl_yosys_plugin=False):
         sources = [
             # Common / Types / Helpers
             "decode_types.vhdl",
@@ -293,7 +294,10 @@ class Microwatt(CPU):
             from litex.build import tools
             import subprocess
             ys = []
-            ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 \\")
+            # ideally this would be some sort of string->(self.parm) mapping.
+            # but I'm not familiar enough with python to do that.
+            vhdl_generics = "-gRESET_ADDRESS=" + str(self.reset_address) + " "
+            ys.append("ghdl --ieee=synopsys -fexplicit -frelaxed-rules --std=08 " + vhdl_generics + "\\")
             for source in sources:
                 ys.append(os.path.join(sdir, source) + " \\")
             ys.append(os.path.join(os.path.dirname(__file__), "microwatt_wrapper.vhdl") + " \\")

litex/soc/cores/cpu/microwatt/microwatt_wrapper.vhdl

@@ -12,6 +12,7 @@ use work.wishbone_types.all;
 
 entity microwatt_wrapper is
     generic (
+        RESET_ADDRESS   : std_ulogic_vector(63 downto 0) := (others => '0');
         SIM             : boolean := false;
         DISABLE_FLATTEN : boolean := false
     );
@@ -90,6 +91,7 @@ begin
 
     microwatt_core : entity work.core
         generic map (
+            RESET_ADDRESS   => RESET_ADDRESS,
             SIM             => SIM,
             DISABLE_FLATTEN => DISABLE_FLATTEN
         )