Commit 53a567da authored by bunnie's avatar bunnie

wire up missing register bits.

Not sure how they went missing...but just noticed them.
parent 63c19ff4
......@@ -283,10 +283,12 @@ class S7I2S(Module, AutoCSR, AutoDoc):
o_WRERR = rx_wrerr,
)
self.comb += [ # Wire up the status signals and interrupts
self.rx_stat.fields.overflow.eq(rx_wrerr),
self.rx_stat.fields.underflow.eq(rx_rderr),
self.rx_stat.fields.dataready.eq(rx_almostfull),
self.rx_stat.fields.wrcount.eq(rx_wrcount),
self.rx_stat.fields.rdcount.eq(rx_rdcount),
self.rx_stat.fields.empty.eq(rx_empty),
self.ev.rx_ready.trigger.eq(rx_almostfull),
self.ev.rx_error.trigger.eq(rx_wrerr | rx_rderr),
]
......
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