Commit 51f2e6ce authored by Florent Kermarrec's avatar Florent Kermarrec

build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput.

parent 23dfefb9
......@@ -81,8 +81,8 @@ class InferedSDRTristate(Module):
_o = Signal()
_oe = Signal()
_i = Signal()
self.specials += SDROutput(o, _o)
self.specials += SDRInput(_i, i)
self.specials += SDROutput(o, _o, clk)
self.specials += SDRInput(_i, i, clk)
self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain)
self.specials += Tristate(io, _o, _oe, _i)
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