Commit 4b6ad8aa authored by Florent Kermarrec's avatar Florent Kermarrec

build/sim: allow defining start/end cycles for tracing

parent ecb60f6e
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#include <verilated.h> #include <verilated.h>
VerilatedVcdC* tfp; VerilatedVcdC* tfp;
long tfp_start;
long tfp_end;
extern "C" void litex_sim_eval(void *vdut) extern "C" void litex_sim_eval(void *vdut)
{ {
...@@ -22,9 +24,11 @@ extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]) ...@@ -22,9 +24,11 @@ extern "C" void litex_sim_init_cmdargs(int argc, char *argv[])
Verilated::commandArgs(argc, argv); Verilated::commandArgs(argc, argv);
} }
extern "C" void litex_sim_init_tracer(void *vdut) extern "C" void litex_sim_init_tracer(void *vdut, long start, long end)
{ {
Vdut *dut = (Vdut*)vdut; Vdut *dut = (Vdut*)vdut;
tfp_start = start;
tfp_end = end;
Verilated::traceEverOn(true); Verilated::traceEverOn(true);
tfp = new VerilatedVcdC; tfp = new VerilatedVcdC;
dut->trace(tfp, 99); dut->trace(tfp, 99);
...@@ -34,7 +38,15 @@ extern "C" void litex_sim_init_tracer(void *vdut) ...@@ -34,7 +38,15 @@ extern "C" void litex_sim_init_tracer(void *vdut)
extern "C" void litex_sim_tracer_dump() extern "C" void litex_sim_tracer_dump()
{ {
static unsigned int ticks=0; static unsigned int ticks=0;
tfp->dump(ticks++); int dump = 1;
if (ticks < tfp_start)
dump = 0;
if (tfp_end != -1)
if (ticks > tfp_end)
dump = 0;
if (dump)
tfp->dump(ticks);
ticks++;
} }
extern "C" int litex_sim_got_finish() extern "C" int litex_sim_got_finish()
......
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
#ifdef __cplusplus #ifdef __cplusplus
extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]); extern "C" void litex_sim_init_cmdargs(int argc, char *argv[]);
extern "C" void litex_sim_eval(void *vdut); extern "C" void litex_sim_eval(void *vdut);
extern "C" void litex_sim_init_tracer(void *vdut); extern "C" void litex_sim_init_tracer(void *vdut, long start, long end)
extern "C" void litex_sim_tracer_dump(); extern "C" void litex_sim_tracer_dump();
extern "C" int litex_sim_got_finish(); extern "C" int litex_sim_got_finish();
#if VM_COVERAGE #if VM_COVERAGE
......
...@@ -60,7 +60,7 @@ def _generate_sim_cpp_struct(name, index, siglist): ...@@ -60,7 +60,7 @@ def _generate_sim_cpp_struct(name, index, siglist):
return content return content
def _generate_sim_cpp(platform, trace=False): def _generate_sim_cpp(platform, trace=False, trace_start=0, trace_end=-1):
content = """\ content = """\
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
...@@ -69,7 +69,7 @@ def _generate_sim_cpp(platform, trace=False): ...@@ -69,7 +69,7 @@ def _generate_sim_cpp(platform, trace=False):
#include <verilated.h> #include <verilated.h>
#include "dut_header.h" #include "dut_header.h"
extern "C" void litex_sim_init_tracer(void *vdut); extern "C" void litex_sim_init_tracer(void *vdut, long start, long end);
extern "C" void litex_sim_tracer_dump(); extern "C" void litex_sim_tracer_dump();
extern "C" void litex_sim_dump() extern "C" void litex_sim_dump()
...@@ -80,17 +80,17 @@ extern "C" void litex_sim_dump() ...@@ -80,17 +80,17 @@ extern "C" void litex_sim_dump()
litex_sim_tracer_dump(); litex_sim_tracer_dump();
""" """
content += """\ content += """\
} }}
extern "C" void litex_sim_init(void **out) extern "C" void litex_sim_init(void **out)
{ {{
Vdut *dut; Vdut *dut;
dut = new Vdut; dut = new Vdut;
litex_sim_init_tracer(dut); litex_sim_init_tracer(dut, {},{});
""" """.format(trace_start, trace_end)
for args in platform.sim_requested: for args in platform.sim_requested:
content += _generate_sim_cpp_struct(*args) content += _generate_sim_cpp_struct(*args)
...@@ -169,7 +169,8 @@ def _run_sim(build_name, as_root=False): ...@@ -169,7 +169,8 @@ def _run_sim(build_name, as_root=False):
class SimVerilatorToolchain: class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="dut", def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", build=True, run=True, threads=1, toolchain_path=None, serial="console", build=True, run=True, threads=1,
verbose=True, sim_config=None, trace=False, coverage=False): verbose=True, sim_config=None, coverage=False,
trace=False, trace_start=0, trace_end=-1):
# create build directory # create build directory
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
...@@ -191,7 +192,7 @@ class SimVerilatorToolchain: ...@@ -191,7 +192,7 @@ class SimVerilatorToolchain:
# generate cpp header/main/variables # generate cpp header/main/variables
_generate_sim_h(platform) _generate_sim_h(platform)
_generate_sim_cpp(platform, trace) _generate_sim_cpp(platform, trace, trace_start, trace_end)
_generate_sim_variables(platform.verilog_include_paths) _generate_sim_variables(platform.verilog_include_paths)
# generate sim config # generate sim config
......
...@@ -200,6 +200,10 @@ def main(): ...@@ -200,6 +200,10 @@ def main():
help="enable Analyzer support") help="enable Analyzer support")
parser.add_argument("--trace", action="store_true", parser.add_argument("--trace", action="store_true",
help="enable VCD tracing") help="enable VCD tracing")
parser.add_argument("--trace-start", default=0,
help="cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1,
help="cycle to end VCD tracing")
args = parser.parse_args() args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args) soc_kwargs = soc_sdram_argdict(args)
...@@ -237,10 +241,12 @@ def main(): ...@@ -237,10 +241,12 @@ def main():
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000) soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder_kwargs["csr_csv"] = "csr.csv" builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs) builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace) vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
if args.with_analyzer: if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv") soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False, threads=args.threads, sim_config=sim_config, trace=args.trace) builder.build(build=False, threads=args.threads, sim_config=sim_config,
trace=args.trace, trace_start=int(args.trace_start), trace_end=int(args.trace_end))
if __name__ == "__main__": if __name__ == "__main__":
......
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