integration/soc/sdcard: add mode parameter to enable read only, write only or read+write modes.

litex/soc/integration/soc.py

@@ -1244,7 +1244,8 @@ class LiteXSoC(SoC):
         self.add_csr(name)
 
     # Add SDCard -----------------------------------------------------------------------------------
-    def add_sdcard(self, name="sdcard", use_emulator=False):
+    def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False):
+        assert mode in ["read", "write", "read+write"]
         # Imports
         from litesdcard.emulator import SDEmulator
         from litesdcard.phy import SDPHY
@@ -1266,15 +1267,17 @@ class LiteXSoC(SoC):
         self.add_csr("sdcore")
 
         # Block2Mem DMA
-        bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
-        self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
-        self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
-        self.bus.add_master("sdblock2mem", master=bus)
-        self.add_csr("sdblock2mem")
+        if "read" in mode:
+            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
+            self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
+            self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
+            self.bus.add_master("sdblock2mem", master=bus)
+            self.add_csr("sdblock2mem")
 
         # Mem2Block DMA
-        bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
-        self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
-        self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
-        self.bus.add_master("sdmem2block", master=bus)
-        self.add_csr("sdmem2block")
+        if "write" in mode:
+            bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
+            self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
+            self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
+            self.bus.add_master("sdmem2block", master=bus)
+            self.add_csr("sdmem2block")

litex/soc/software/bios/cmds/cmd_litesdcard.c

@@ -27,7 +27,7 @@ define_command(sdinit, sdcard_init, "Initialize SDCard", LITESDCARD_CMDS);
  * Perform SDcard block read
  *
  */
-#ifdef CSR_SDCORE_BASE
+#ifdef CSR_SDBLOCK2MEM_BASE
 static void sdread(int nb_params, char **params)
 {
 	unsigned int block;
@@ -58,7 +58,7 @@ define_command(sdread, sdread, "Read SDCard block", LITESDCARD_CMDS);
  * Perform SDcard block write
  *
  */
-#ifdef CSR_SDCORE_BASE
+#ifdef CSR_SDMEM2BLOCK_BASE
 static void sdwrite(int nb_params, char **params)
 {
 	int i;

litex/soc/software/liblitesdcard/sdcard.c

@@ -555,6 +555,8 @@ int sdcard_init(void) {
 	return 1;
 }
 
+#ifdef CSR_SDBLOCK2MEM_BASE
+
 void sdcard_read(uint32_t sector, uint32_t count, uint8_t* buf)
 {
 	/* Initialize DMA Writer */
@@ -581,6 +583,10 @@ sdcard_set_block_count(count);
 #endif
 }
 
+#endif
+
+#ifdef CSR_SDMEM2BLOCK_BASE
+
 void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf)
 {
 	while (count--) {
@@ -606,6 +612,7 @@ void sdcard_write(uint32_t sector, uint32_t count, uint8_t* buf)
 		sector += 1;
 	}
 }
+#endif
 
 /*-----------------------------------------------------------------------*/
 /* SDCard FatFs disk functions                                           */