Unverified Commit 408d3f1f authored by enjoy-digital's avatar enjoy-digital Committed by GitHub

Merge pull request #201 from gsomlo/gls-fix-initmem

tools/litex_sim: fix default endianness for mem_init
parents f47b4902 ab827d21
...@@ -214,10 +214,10 @@ def main(): ...@@ -214,10 +214,10 @@ def main():
sim_config = SimConfig(default_clk="sys_clk") sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial") sim_config.add_module("serial2console", "serial")
cpu_endianness = "big" cpu_endianness = "little"
if "cpu_type" in soc_kwargs: if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]: if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
cpu_endianness = "little" cpu_endianness = "big"
if args.rom_init: if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness) soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
......
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