Commit 3df2e3f7 authored by Timothy Pearson's avatar Timothy Pearson

Merge branch 'meklort/xics-swap' into 'master'

xics: Disable endianness swapping

See merge request kestrel-collaboration/kestrel-litex/litex!1
parents 298c8559 af816563
......@@ -17,22 +17,12 @@ from litex.soc.cores.cpu import CPU
CPU_VARIANTS = ["standard", "standard+ghdl"]
class XICSSlave(Module, AutoCSR):
def __init__(self, platform, core_irq_out=Signal(), int_level_in=Signal(16), endianness="big", variant="standard"):
def __init__(self, platform, core_irq_out=Signal(), int_level_in=Signal(16), variant="standard"):
self.variant = variant
self.icp_bus = icp_bus = wishbone.Interface(data_width=32, adr_width=12)
self.ics_bus = ics_bus = wishbone.Interface(data_width=32, adr_width=12)
# Bus endianness handlers
self.icp_dat_w = Signal(32)
self.icp_dat_r = Signal(32)
self.comb += self.icp_dat_w.eq(icp_bus.dat_w if endianness == "big" else reverse_bytes(icp_bus.dat_w))
self.comb += icp_bus.dat_r.eq(self.icp_dat_r if endianness == "big" else reverse_bytes(self.icp_dat_r))
self.ics_dat_w = Signal(32)
self.ics_dat_r = Signal(32)
self.comb += self.ics_dat_w.eq(ics_bus.dat_w if endianness == "big" else reverse_bytes(ics_bus.dat_w))
self.comb += ics_bus.dat_r.eq(self.ics_dat_r if endianness == "big" else reverse_bytes(self.ics_dat_r))
# XICS signals
self.ics_icp_xfer_src = Signal(4)
self.ics_icp_xfer_pri = Signal(8)
......@@ -43,11 +33,11 @@ class XICSSlave(Module, AutoCSR):
i_rst = ResetSignal(),
# Wishbone bus
o_wishbone_dat_r = self.icp_dat_r,
o_wishbone_dat_r = icp_bus.dat_r,
o_wishbone_ack = icp_bus.ack,
i_wishbone_adr = icp_bus.adr,
i_wishbone_dat_w = self.icp_dat_w,
i_wishbone_dat_w = icp_bus.dat_w,
i_wishbone_cyc = icp_bus.cyc,
i_wishbone_stb = icp_bus.stb,
i_wishbone_sel = icp_bus.sel,
......@@ -65,11 +55,11 @@ class XICSSlave(Module, AutoCSR):
i_rst = ResetSignal(),
# Wishbone bus
o_wishbone_dat_r = self.ics_dat_r,
o_wishbone_dat_r = ics_bus.dat_r,
o_wishbone_ack = ics_bus.ack,
i_wishbone_adr = ics_bus.adr,
i_wishbone_dat_w = self.ics_dat_w,
i_wishbone_dat_w = ics_bus.dat_w,
i_wishbone_cyc = ics_bus.cyc,
i_wishbone_stb = ics_bus.stb,
i_wishbone_sel = ics_bus.sel,
......@@ -239,8 +229,7 @@ class Microwatt(CPU):
platform = self.platform,
variant = self.variant,
core_irq_out = self.core_ext_irq,
int_level_in = self.interrupt,
endianness = self.endianness)
int_level_in = self.interrupt)
@staticmethod
def add_sources(platform, use_ghdl_yosys_plugin=False):
......
......@@ -31,6 +31,8 @@ void isr(uint64_t vec);
// Default external interrupt priority set by software during IRQ enable
#define PPC_EXT_INTERRUPT_PRIO 0x08
#define bswap32(x) (uint32_t)__builtin_bswap32((uint32_t)(x))
uint8_t inline xics_icp_readb(int reg)
{
return *((uint8_t*)(HOSTXICSICP_BASE + reg));
......@@ -43,22 +45,22 @@ void inline xics_icp_writeb(int reg, uint8_t value)
uint32_t inline xics_icp_readw(int reg)
{
return *((uint32_t*)(HOSTXICSICP_BASE + reg));
return bswap32(*((uint32_t*)(HOSTXICSICP_BASE + reg)));
}
void inline xics_icp_writew(int reg, uint32_t value)
{
*((uint32_t*)(HOSTXICSICP_BASE + reg)) = value;
*((uint32_t*)(HOSTXICSICP_BASE + reg)) = bswap32(value);
}
uint32_t inline xics_ics_read_xive(int irq_number)
{
return *((uint32_t*)(HOSTXICSICS_BASE + 0x800 + (irq_number << 2)));
return bswap32(*((uint32_t*)(HOSTXICSICS_BASE + 0x800 + (irq_number << 2))));
}
void inline xics_ics_write_xive(int irq_number, uint32_t priority)
{
*((uint32_t*)(HOSTXICSICS_BASE + 0x800 + (irq_number << 2))) = priority;
*((uint32_t*)(HOSTXICSICS_BASE + 0x800 + (irq_number << 2))) = bswap32(priority);
}
void inline mtmsrd(uint64_t val)
......
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