Commit 1f27b740 authored by Florent Kermarrec's avatar Florent Kermarrec

soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing.

parent 408d1a9f
......@@ -1299,7 +1299,10 @@ class LiteXSoC(SoC):
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
self.bus.add_master("sdblock2mem", master=bus)
if hasattr(self.cpu, "dmabus"): # FIXME: VexRiscv SMP / DMA test.
self.submodules += wishbone.Converter(bus, self.cpu.dmabus)
else:
self.bus.add_master("sdblock2mem", master=bus)
self.add_csr("sdblock2mem")
# Mem2Block DMA
......
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