Commit 07bc589c authored by Jędrzej Boczar's avatar Jędrzej Boczar

fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed

Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
https://github.com/antmicro/litex-buildenv/commit/cc003bef3ac1407f9788ec8b7cc52d5981f8364a
and litex bumped to 4a18b828,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
parent 4a18b828
...@@ -282,12 +282,15 @@ class SoCBusHandler(Module): ...@@ -282,12 +282,15 @@ class SoCBusHandler(Module):
assert direction in ["m2s", "s2m"] assert direction in ["m2s", "s2m"]
if isinstance(interface, wishbone.Interface): if isinstance(interface, wishbone.Interface):
new_interface = wishbone.Interface(data_width=self.data_width) if interface.data_width != self.data_width:
if direction == "m2s": new_interface = wishbone.Interface(data_width=self.data_width)
converter = wishbone.Converter(master=interface, slave=new_interface) if direction == "m2s":
if direction == "s2m": converter = wishbone.Converter(master=interface, slave=new_interface)
converter = wishbone.Converter(master=new_interface, slave=interface) if direction == "s2m":
self.submodules += converter converter = wishbone.Converter(master=new_interface, slave=interface)
self.submodules += converter
else:
new_interface = interface
elif isinstance(interface, axi.AXILiteInterface): elif isinstance(interface, axi.AXILiteInterface):
# Data width conversion # Data width conversion
intermediate = axi.AXILiteInterface(data_width=self.data_width) intermediate = axi.AXILiteInterface(data_width=self.data_width)
......
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