• Gabriel L. Somlo's avatar
    tools/litex_sim: fix default endianness for mem_init · ab827d21
    Gabriel L. Somlo authored
    Initializing ROM and/or RAM content requires knowing the CPU
    endianness before the SimSoC->SoCSDRAM->SoCCore constructor
    sequence is invoked (before the SoC's self.cpu.endianness
    could be accessed). Given that the majority of supported CPU
    models use "little", set it as the new default, and override
    only for the two models that use "big" endianness.
litex_sim.py 9.23 KB