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Florent Kermarrec authored
- do the CSR alignment update only if CPU is not CPUNone. - revert PointToPoint interconnect when 1 master and 1 slave since this will break others use cases and will prevent mapping slave to a specific location. It's probably better to let the synthesis tools optimize the 1:1 mapping directly. - add with_soc_interconnect parameter to add_sdram that defaults to True. When set to False, only the LiteDRAMCore will be instantiated and interconnect with the SoC will not be added.
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